ISSCC 2019 / SESSION 18 / ANALOG TECHNIQUES / 18.
18.7 A 0.7V, 2.35% 3σ-Accuracy Bandgap Reference in 12nm
CMOS
Yi-Wen Chen, Jaw-Juinn Horng, Chin-Ho Chang, Amit Kundu,
Yung-Chow Peng, Mark Chen
TSMC, Hsinchu, Taiwan
Bandgap reference (BGR) circuits are widely used due to their stable output
voltage over process, supply voltage and temperature variations. Reference
voltage stability is critical for data-acquisition applications and lower supply
voltages can reduce the power of mixed-signal systems. However BGR for analog
circuits is one of the bottlenecks for sub-1V supply operation because BGR supply
voltage is limited by VEB+VDS [1]. VEB refers to the emitter-base voltage of a pnp
transistor which is limited to ~0.6 to 0.7V due to silicon junction cut-in voltage,
while VDS is the drain-source saturation voltage of a current-mirror. The BGR
temperature dependence is decided by the weighted sum of proportional-to-
absolute-temperature(PTAT) and complementary-to-absolute-temperature (CTAT)
terms. An alternative PTAT generator can be implemented by dVGS (gate-to-source
voltage difference) of a MOS pair in subthreshold [2]. The CTAT generator can be
implemented by special devices or using the gate-source voltage VGS of
subthreshold MOSFETs. Although the VGS of a subthreshold MOSFET is smaller
than emitter-base voltage of a pnp transistor, the MOSFET model inaccuracy in
the subthreshold region and high process-dependent characteristic of MOSFET
gate-source voltage induces high variation for voltage reference circuits.
A sampled BGR [3] uses a capacitive voltage divider to divide the output voltage
of the bipolar transistor without resistors and it achieves sub-1V operation. A 2×-
charge-pump-based BGR [4] further pumps the supply voltage to enable 0.5V
operation. However both structures need switched-capacitor circuits, which
creates output ripple and is hence a major design trade-off in high-accuracy data
converters.
Figure 18.7.1 shows the measured values of VEB and dVEB (emitter-to-base voltage
difference) at 25°C and -40°C at different bias currents. The data was obtained
from 35 pairs of nominally identical BJTs (emitter areas of ~3um2), which were
biased at a current density ratio of 15:1. VEB is decided by the design trade-off
between bias current, minimum operating temperature and supply voltage. Lower
supply voltage needs a lower and stable VEB using small BJT bias current and also
needs to consider the operating temperature range. Figure 18.7.1 also shows not
only that the BJT has larger VEB and dVEB variation at lower bias current but also
MOS current-mirror mismatch is increased due to subthreshold operation. If the
VEB at -40°C decreases from 0.9V to 0.6V by reducing the BJT bias current from
10uA to a few nanoamps for low-supply-voltage application, the current mirror
area blows up by 16× to meet the current-mirror matching requirement of a 3%
3σ output accuracy. A large value of resistance is also needed to provide low bias
current, which costs additional silicon area. Although BJT bias current density
can be reduced by modifying the 1:N BJT array to M:N×M BJT arrays to relax
current-mirror and resistance area, BJT array area will increase. As a result, there
is an area trade-off among current-mirror, BJT array and resistor array choices.
Figure 18.7.2 shows the proposed Bandgap circuit diagram, which is composed
of a current-mode Bandgap and an automatic current-controlled feedback loop.
The automatic current-controlled feedback loop is composed of a current mirror,
an opamp and a resistor. Through the opamp negative feed-back characteristic,
the voltage drop across R5 is the difference between VEB(Q1) and VEB(Q2), defining
the current as dVEB/R5. Since voltage drop across R3 is also dVEB, the current
flowing into the feedback loop can be derived as (R3/R5)∙IR3. Therefore, the BJT
current is controlled well by resistor ratio so as to let the BJT mismatch be fixed
even for a lower bias-current range. Meanwhile, the opamp in the feedback loop
produces a feedback signal to both of its inputs. An overall negative feedback is
ensured since M5 output resistance is Rds(M5)//(R5+RQ1//R1//Rds(M1)) and M4 output
resistance is Rds(M4)//(RQ2//(R3+(R2//Rds(M2)))), and negative-feedback loop gain is
larger than positive- feedback loop gain due to R5. Figure 18.7.3 shows the Bode
plot of the automatic current-controlled feedback loop. The DC gain is 52.8dB
with a phase margin of 45°. With the automatic current-controlled feedback loop,
the current flowing into the BJT array is well controlled for low supply voltage
operation and prohibits the current-mirror MOS to enter the subthreshold region
without increasing the MOS size and thus ensuring good mismatch performance.
306 • 2019 IEEE International Solid-State Circuits Conference
Figure 18.7.3 also shows the output-variation breakdown chart of the proposed
Bandgap. The dominant variation sources are the two current mirrors (M1, M2,
M3 and M4, M5). Both have mismatch values designed at 0.08%. However the
contributed percentages of output variation are 62% and 13% respectively for the
2 aforementioned current mirrors since the current-mirror mismatch in the
automatic current-controlled feedback loop is suppressed by the feedback loop
gain. The sizes of the two current mirrors can be further optimized and their area
can be shrunk further based on the mismatch impact level and current ratio. The
current ratio between the two current mirrors is decided by the resistor ratio of
R5/R3, the temperature sensitivity of PTAT, CTAT voltage and the minimum
supply voltage. It also needs to be mentioned that the 1σ input-offset voltage
variation of the opamp in the automatic current-controlled feedback loop only
contributes 1% of total output variation. The opamp input-offset voltage (VOS)
changes the voltage across R5 from dVEB to dVEB+VOS and consequently current
ratio IR3/IM5 is derived as R5/R3/(1-VOS/dVEB). Since VOS can be easily designed to
be much smaller than dVEB, the impact of the opamp input-offset voltage to the
output variation is almost negligible.
The proposed Bandgap was implemented in 12nm FinFET CMOS technology.
10nA BJT bias current for a 1:15 BJT array was chosen to reduce VEB and 100nA
current in R3 (~900kΩ) is achieved by an R3/R5 ratio of 0.9. This ratio was
selected to reduce total circuit current consumption. However for production
purposes, a higher resistor ratio can be selected for increasing current in R3,
which further mitigates Bandgap output variation and also reduces current-mirror
area. Meanwhile, a current-mirror ratio (M1:M2:M3) of 1:1:1 is used for matching
purposes. With the existing process model, simulation results show that current-
mirror mismatch increases 47% and Bandgap output variation increases 23%
when the automatic current-controlled feedback loop is removed and the current
mirror is directly biased at 10nA.
Figure 18.7.4 shows the on-wafer measured reference output voltages across
temperature from 35 dies of 1 wafer with a 0.7V supply voltage. The untrimmed
measured output voltage from -20°C to 125°C varies from 204mV to 210mV. The
measured temperature coefficient is from 4.9ppm/°C to 82.3ppm/°C and the
average temperature coefficient is 40.51ppm. Figure 18.7.5 shows the measured
distribution diagram of the output voltage at 25°C and 0.7V supply voltage. The
average voltage is 207mV and the standard deviation is 1.63mV, showing a 3σ-
accuracy of 2.35%. The measured 3σ-accuracy at 25°C also shows a constant
value of approximately 2.35% with supply voltage changed from 0.7V to 0.9V.
Figure 18.7.6 compares this work with other state-of-the–art voltage references
that achieve <3.5% 3σ-accuracy. With the proposed automatic-feedback-loop
technique, this BJT-based reference achieves competitive accuracy with a low
supply voltage, while providing a ripple-free reference output voltage. Figure
18.7.7 shows the die micrograph.
References:
[1] H. Banba et al., “A CMOS Bandgap Reference Circuit with Sub-1-V Operation,”
IEEE JSSC, vol. 34, no. 5, pp. 670-674, May 1999.
[2] Y. Osaki et al., “1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply,
52.5-nW, 0.55-V Sub-bandgap Reference Circuits for Nanowatt CMOS LSIs,” IEEE
JSSC, vol. 48, no. 6, pp. 1530-1538, June 2013.
[3] V. Ivanov et al., “An Ultra Low Power Bandgap Operational at Supply from
0.75V,” IEEE JSSC, vol. 47, no. 7, pp. 1515-1523, July 2012.
[4] A. Shrivastava et al., “A 32nW Bandgap Reference Voltage Operational from
0.5V Supply for Ultra-Low Power Systems,” ISSCC, pp. 94-95, Feb. 2015.
[5] Y. Ji et al., “A 9.3nW All-in-One Bandgap Voltage and Current Reference
Circuit,” ISSCC, pp. 100-101, Feb. 2017.
[6] J. M. Lee et al., “A 29nW Bandgap Reference Circuit,” ISSCC, pp. 100-101,
Feb. 2015.
[7] U. Kamath et al., “A 1 V Bandgap Reference in 7-nm FinFET with a
Programmable Temperature Coefficient and an Inaccuracy of ±0.2% from -45°C
to 125°C,” ESSCIRC, pp. 78-81, 2018.
978-1-5386-8531-0/19/$31.00 ©2019 IEEE
 ISSCC 2019 / February 19, 2019 / 4:30 PM

Figure 18.7.1: VEB, dVEB silicon results @25°C, -40°C and simulated current-
mirror mismatch at 25°C. The current-density ratio between BJTs of VEB1 and
VEB2 is 15:1. Figure 18.7.2: Proposed Bandgap circuit diagram.

18

Figure 18.7.3: Stability and output variation sensitivity analysis of proposed Figure 18.7.4: Measured output voltage from 35 dies and the cumulative
Bandgap. distribution of output voltage from -20°C to 125°C.

Figure 18.7.5: Measured distribution diagram of the output voltage at 25°C and
0.7V supply voltage and 3σ-accuracy at 25°C from 0.7V to 0.9V supply voltage. Figure 18.7.6: Measurement summary and comparison table.

DIGEST OF TECHNICAL PAPERS • 307

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Figure 18.7.7: Die micrograph.

• 2019 IEEE International Solid-State Circuits Conference 978-1-5386-8531-0/19/$31.00 ©2019 IEEE