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U. Schwalke1, J. Berthold1, A. Bourenkov2, M. Eisele1, R. Krieg1,
A. Narr3 , D. Schumann1, R. Seibert3 and R. Thanner3
1)
Siemens, Corp. R&D, Microelectronics,
3)
Siemens, Semiconductor Division
81730 Munich, Germany
2)
Fraunhofer-Institut f r Integrierte Schaltungen, FhG IIS-B,
91058 Erlangen, Germany

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The decrease in supply voltage is the most effective approach to reduce power consumption
in CMOS circuits. Accordingly, the ultimate goal for many low-power applications is aimed
at a single-battery operation with a nominal supply voltage of 1.2V and an end-of-life
voltage of 0.9V. On the other hand, circuit performance is often sacrified when supply
voltage (Vdd) is reduced. In order to compensate for the loss in drive current, threshold
voltage (Vth) is reduced. This approach, however, requires an n+/p+ gate technology /1/ with
optimized gate workfunction for N- and PMOS devices to achieve sufficient performance at
low voltage and still maintain good short channel behavior as well as low off-leakage (Ioff).

In this work we report on the realization and evaluation of an ultra low-voltage/low-power

0.25 m (n+/p+) dual-workfunction CMOS technology.

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The process starts with a conventional poly-buffered LOCOS technology for device
isolation followed with retrograde well formation. After growing the thin gate oxide and
after 250nm polySi deposition, gate definition is performed using anti-reflective coatings in

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 no anneal

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combination with i-line lithography. The gates are reoxidized (10nm) and the extensions are
implanted. Since this technology is aimed to operate at a low Vdd, fairly hard (2E14 to
5E14/cm2) extensions for low resistance can be used without deteriorating reliability.
Extensions are fabricated with pockets to improve on Vth roll-off, especially for the PMOS.
In order to keep process complexity low, the high dose n+/p+ S/D implants (5E15/cm2) are
simultaneously used to realize n+/p+ doped gates. This approach, however, requires a
careful optimization of the thermal budget to satisfy both, the junctions (i.e. shallow) and the
gates (i.e. no gate depletion). For this reason the total thermal budget is split between n+
and p+ anneals and optimized to prevent gate depletion (Fig. 1) and boron penetration (Fig.
2). As deduced from CV measurements, the residual gate depletion is at approximately 5 -
8% without degrading shallow S/D junctions. Subsequent processing is fairly conventional,
including Ti-SALICIDE and 2-layer metallization.

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Low voltage CMOS devices were fabricated with gate oxides of 6 to 4.5nm thickness and
compared to the respective device simulation data. An example is given in Fig. 3 for the
NMOS and similar results are obtained for the PMOS. It is quite obvious that for a given
oxide thickness any increase in drain current (Ids) will be at the expense of a larger Ioff.
While this leakage is not a severe concern during circuit operation, the increased Ioff is
undesirable because of stand-by power consumption, especially for battery operated circuits.
Only when the gate oxide thickness is reduced, a gain in drive current can be realized
without increasing Ioff. Furthermore, the subthreshold slope is decreased (e.g. 84 to 76
mV/dec) for the thinner gate oxide which is also beneficial when reducing Vth (Fig.4). The
target oxide thickness of 4.5nm was chosen as a compromise between current drive and
sufficient immunity against direct tunneling.

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 -1
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A 17-stage inverter ring oscillator circuit with FI=FO=2 was used for dynamic performance
evaluation. To ease measurement of the output frequency an 1024 divider output stage is
integrated. At Vdd=1.2V a ring oscillator delay of 100pS/stage is obtained for Tox=4.5nm
which decreases to 48pS/stage at 2.5V. The equivalent oscillating frequencies of the circuit
are 600MHz and 1.2GHz, respectively (Fig. 5). Despite the increase in gate capacitance for
the 4.5nm gate oxide, there is a substantial net gain in dynamic performance. In addition to
ring oscillators, a carry select adder (CSA) circuit /2/ with typical low-voltage relevant data
paths was chosen to demonstrate the potential of the low-voltage technology. Compared to a
conventional 3.3V 0.5 m single-workfunction CMOS reference technology, the power
delay product decreases by 14 times for the low-voltage optimized technology running at
Vdd=1.2V (Fig. 6), while still maintaining same performance (Fig.7). The low-voltage CSA
circuit is fully functional down to Vdd=0.6V.

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Hot-carrier degradation may limit the maximum supply voltage used in this technology.
Since fairly hard extensions have been used, the evaluation of hot carrier reliability of
NMOS and PMOS devices is required. For the NMOS, lifetime was measured at 5%
degradation of Id measured in the reverse mode after single-side (drain) DC stress at Ibmax
and T=25C. The result of degradation measurements are shown in Fig. 8. In the case of the
PMOS, the lifetime degradation at 2% in Vth after single-side DC stress was used. The
extrapolation of the logarithm of the lifetime versus the inverse drain bias reveals sufficient
lifetime margin, even above 2V. Accordingly, during normal battery operation (i.e. up to
1.5V) no reliability problems are expected. In fact, at Vds=1.2V the extrapolated lifetime is
greater than 50 years. These results suggest, that some of the reliability margin can be traded
against performance by further reducing junction resistance or channel length.

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We have developed an ultra low-power/low-voltage 0.25 m CMOS technology with
optimized gate workfunction (n+/p+) for high performance at low power consumption.
Using a 24bit CSA circuit for realistic evaluation of performance and energy efficiency, the
potential of this technology to complement existing CMOS technologies without sacrificing
on performance is demonstrated. These improvements were achieved without increasing
process complexity or deteriorating hot-carrier reliability.

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This work was performed within the ESPRIT ADEQUAT+ Project on Low-Voltage 0.25 m CMOS
Technology and was supported by the European Union (JESSI BT111-ESPRIT 21752).

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/1/ U. Schwalke et al., SSDM Extended Abstracts, p. 309 (1990)
/2/ M. Eisele et al., Tech. Digest of the International Symposium on Low Power Electronics and
Design, p. 237 (1996).

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