CHARACTERIZATION AND MODELING OF FREQUENCY DISPERSION

IN AMORPHOUS SILICON THIN FILM TRANSISTORS

H. C. SLADEa'b, M. S. SHURa, AND T. YTTERDALa

a Rensselaer Polytechnic Institute, ECSE Dept., Troy, NY 12180
b University of Virginia, Electrical Engineering, Thornton Hall, Charlottesville, VA 22903-2442

ABSTRACT

The large number of localized energy states in amorphous and polysilicon thin film
transistors causes non-crystalline effects in both the DC and AC transistor characteristics. The
observed frequency dispersion of the device capacitances is linked to the characteristic times of
electron trapping and emission from localized thin film transistors and is modeled analytically by
introducing effective RC time constants, which are proportional to the electron transit times,
determined by the field effect mobility. The small-signal gate-to-source and gate-to-drain
capacitances have been derived using Meyer's approach, which takes into account the non-zero
drain-source voltage to achieve a partitioning of the channel capacitance. We have verified the
model for amorphous silicon thin film transistors for varying gate lengths and frequencies.

INTRODUCTION

The prominence of hydrogenated amorphous silicon (a-Si:H) and polysilicon (poly-Si)

thin film transistors (TFTs) and the emergence of polymer TFTs has stimulated an interested in
studying non-crystalline, non-ideal effects in field effect transistors. The results of these studies
are needed both for modeling TFTs (see, for example, the companion paper [1]) and also may
find application in ultra-short-channel crystalline devices, such as deep submicron Si
MOSFETS.
As shown in Fig. 1, there are marked differences in the transfer characteristics for
crystalline silicon MOSFETs, polysilicon TFTs, and amorphous silicon TFTs. At large negative
gate biases, the leakage current dominates. In this region, the high resistance of the intrinsic
amorphous silicon creates very low TFT leakage currents which vary with gate and drain bias.
In contrast, the polysilicon TFT leakage current shows a much larger increase with gate bias and
with drain bias. The crystalline MOSFET has much higher leakage currents due to the
availability of holes.
At higher gate biases, the TFTs move into the subthreshold regime, where the current
increases exponentially with increasing gate bias. The MOSFET has a much steeper
subthreshold slope (approximately 0.1 V/decade) compared to both the poly-Si and a-Si:H TFTs
(approximately 1-1.5 V/decade for the data presented). This is a direct result of the density of
localized states present in the grain boundaries of the poly-Si and throughout the a-Si:H bulk.
The above threshold current in the crystalline MOSFET is also much higher, since all carriers
induced into the channel by the gate voltage are free to conduct charge and the band mobility is
much higher. In the a-Si:H and poly-Si transistors, a large fraction of the induced charge is
trapped, which can be accounted for by introducing a gate-bias-dependent field effect mobility.
Using this approach, we have incorporated the effect of the density of localized states in SPICE
models for the DC TFT operation for both a-Si:H and poly-Si TFTs . In this paper, we address
the effect of the localized states on the capacitance-voltage characteristics for a-Si:H TFTs. A
similar model has been reported for poly-Si TFTs [2].

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Mat. Res. Soc. Symp. Proc. Vol. 467 01997 Materials Research Society
 10~-' I0-i

7
to- -

S10-11
Vd.0- 01,11.51 10., V) VdO-50
U U

to-1310-13
-5 0 5 10 15 20 -5 0 5 10 15 20
Gate Bias tVI Gate Bias tV]
(a) 10z Vd =-3.0V (b)
100 , U

2 0.05 V
a o' A
S10.
10.6
10

10"10 . gate-source voltage (V)

-0,2 0.2 0.6 1.0 1.4 1.8
(c)
Figure 1: Gate transfer characteristics for (a) a polysilicon TFT. (b) an amorphous silicon TFT, and
(c) a crystalline silicon MOSFET. The presence of localized states in the film decreaases the above
threshold current, reduces the subthreshold slope, and decreases the leakage current.

FREQUENCY DISPERSION OF C(V)

The effect of the density of states is even more apparent in the capacitance-voltage
characteristics of the TFTs. The trapping/detrapping effects cause frequency dispersion in the
TFT even at relatively low frequencies, compared to MOSFETs. When the measurement
frequency becomes comparable to the inverse transit time of a carrier in the channel, the finite
charging time of the channel region must be taken into account. Fig. 2 (a) shows the results of
2D simulations of the gate-to-channel capacitance (Cgc(Vgs)) for a crystalline TFT structure (no
localized states) and for a TFT structure with a density of localized states shown in Fig. 2 (b).
The simulations were performed at varying frequencies (f = 100 Hz - 1 MHz) for each device,
but only the non-crystalline TFT exhibits frequency dispersion. The left shift of the
characteristics as frequency is decreased is due to deep state trapping, and stretch out at high
frequencies is due to tail state trapping. The severity of the dispersion is determined by the
number of trapping states in the non-crystalline film and by the gate length. This is supported by
the experimental data for both poly-Si (L = 50 gim) and a-Si:H (L = 60 gim) TFTs shown in Fig. 3
(a) and (b), respectively. The Cgc(Vgs) characteristics for the poly-Si TFT shows significant
stretch-out at 10 MHz and a left shift of the characteristics as the frequency is reduced. In
comparison, the a-Si:H TFT characteristics begin to stretch out at much lower frequencies due to
the much higher density of localized states in the channel region.

882
 2.5
21
20
2.0
Q 19
C> 18
l 1.5 E
0 17
U U 16
2 1.0
15

14-
00.0 2.0 4.0 8.0 Ev E - Ev [eV] Ec
Gate Voltage [Voltsl
(a) (b)
Figure 2: 2D simulations of Cgc(Vgs) for an amorphous silicon TFT (solid lines) and for a crystal-
line-like TFl (dotted lines). The crystalline TFT characteristics do not change with increasing fre-
quency, while the a-Si:H TFT characteristics exhibit strong frequency dispersion. (b) Density of
electronic states for hydrogenated amorphous silicon. Exponentials represent the deep and tail
states for both donor- and acceptor-like traps[4].

SMALL SIGNAL CIRCUIT MODEL

The TFT channel can be considered a transmission line, as proposed by Greve and Hay
[6] and shown in Fig. 4 (a). This can be approximated by placing fractions of the channel
resistance in series with the channel capacitances, as shown in Fig. 4 (b). While this approach
approximates the intuitively satisfying transmission line formalism of [6], it introduces no
additional subtransistors, which dramatically increases the simulation time [7]. We propose a
much simpler (but nearly as accurate) lumped element circuit model, similar to that proposed for
poly-Si TFTs in [2].

1.010 1.001.0
........... ..:. ....
0.80 Max 0.8

~0.60 0 .

Cj0.400.

0.,o -/ . 0.0_
oae Bi MV
(a)
Figure 3: Gate-to-channel capacitance-voltage characteristics for (a) a polysilicon TFl [5) and (b)
and amorphous silicon TFT. The larger density of states in the a-Si:H TFT results in larger disper-
sion.

883
 Q-s -r r)-;.T

TGate
n+ a-Si:H IM
aSl rCdx
thinfl CsX Cd

gate
nitride • Source Rch• Drain
lauer 2 Cs

Cc= SX
ge corsC2
s)+
Gate

(a) (b)
Figure 4: (a) Tranmission line representation of the a-Si:H TFT channel. (b) Small signal model,
which approximates the full transmission line by incorporating access resistors which are a con-
stant fraction of the channel resistance. Both approaches take into account the finite channel charg-
ing time.

We define the channel resistance, Rch, which takes into account the length dependence and the
localized states, as

RCh = [d-d] (1)

V Vs

We introduce the access resistors, which are constant fractions of the channel resistance, by
= Krdx = K2)
rd sslv d=o dxkj
Vd, = 0Vd,
where Kss is a small signal constant simliar to the Elmore constant used in BSIM3v3 non-quasi-
static equivalent circuit model [7] Because rsx physically originates near the source, it is
calculated using Vds = OV.
The small-signal gate-to-source and gate-to-drain capacitances can be derived using
Meyer's approach, which takes into account the non-zero drain-source voltage to achieve a
partitioning of Cgc. The expressions for the access capacitors are

Csx = - (Ccg)DC
22 [
D1 03X I 12- (2(V
VgT_Vdse)) 2s
2(d)
2]

Cd (Ccg)DCjv. 1..(2Vr_ Vs) 2 ~ (4)

where VgT = Vg - VTO and VTO is the threshold voltage defined in [1]. Vase modulates between the
linear and saturation regimes as given by

- Vds (5)
- +dse
(Vdsm) l/msa

YVsat>)

884
and where (Cgc)DC is the DC value of the gate-to-channel capacitance, given by
CiLW
I - o (6"•
' gcDC I +Vdse_
1 xp(
+ 2 VTO)
11Vth

The ideality factor is determined empirically as r1o = flO + 1l0 oVdse, which saturates according to
Eq. (5) where Ci is the maximum capacitance set by the gate insulator. This expression is valid
both above and below threshold and has been derived using the Unified Charge Control Model
for a crystalline silicon MOSFET [8]. The charge saturation voltage, Vsat = Vg, - VTO, which is

1.0 1.0

0.8

S0.6
U,.
U S0.4

0.2

no L.
"-0 2.5 5 7.5 10 12.5 15 "''0 2.5 5 7.5 10 12.5 15
Drain Voltage [Volts] Drain Voltage [Volts]
(a) (b)
Figure 5: Cgd(Vds) for an a-Si:H TFT (W/L = 150/60) Vgs = 0, 5, 10, and 15 V [9]. As the TFT sat-
urates, the Cgd values drop to zero. The transient parameters are Ks, = 5.0, -no = 6, sioo = 20 (a)f-
10 kHz, (b)f= 100 kHz.

0.5

S0.4
0.3
C..)
0-
C..
U 0.2 * Vd,=OV
a Vds=5V
0.1 A Vdh=1OV

0.0
5 7.5 10 12.5 15 "0 2.5 5 7.5 10 12.5 15
Gate Voltage [Volts] Gate Voltage [Volts]

Figure 6: CgI(Vg,) for an a-Si:H TFl (W/L = 150/30) Vd, = 0, 5, 10 V [9]. At low drain biases, Cgs
approcahes 1/2 Cgc. At high drain biases, Cgs approaches 2/3 Cgc. The transient parameters are
KsS = 5.0,71"0o= 6 (a)f= 10 kHz, (b)f= 100 kHz.

885
the pinch-off point for crystalline MOSFETs. However, it is important to note that the TFT
current does not saturate at the same point (see [1]), since, because of the localized states which
trap most of the free chrage, the localized charge can still respond to the AC signal after the
current has saturated.
Measured and modeled Cgd(Vds) characteristics for varying Vg, andf= 10 kHz and 100
kHz are shown in Fig. 5. Measured and modeled Cgs(Vgs) characteristics for varying Vds and f=
10 kHz and 100 kHz are shown in Fig. 6. The capacitance parameters are identical in both cases,
for two different gate lengths. The accuracy is good over a large voltage range and frequency
range. This model will be incorporated into the circuit simulator AIM-Spice [10].

CONCLUSIONS

Non-crystalline transistors are affected in all regimes of operation by the density of

localized states due to the disorder in the semiconductor film. We have presented an analytic
model for the AC characterisitcs of amorphous silicon TFTs which takes into account the
frequency dispersion of the TFT characteristics. The model uses a lumped element small signal
circuit to approximate a transmission line, resulting in frequency dependent Cgs and Cgd
characteristics. This approach models experimental data over a large voltage range and
frequency range with good accuracy.

ACKNOWLEDGEMENTS
The authors gratefully acknowledge the support of the Advanced Research Projects
Agency and would like to thank Mark Jacunski at the University of Virginia for useful
discussions and Rene Lujan at Xerox PARC for sample preparation. Holly Slade would like to
thank the Achievement Rewards for College Scientists (ARCS) Foundation for fellowship
support.

REFERENCES
[1] M. S. Shur, H.C. Slade, T. Ytterdal, L. Wang, Z. Xu, M. Hack, K. Aflatooni, Y Byun, Y.
Chen, M. Froggatt, A. Krishnan, P. Mei, H. Meiling, B.-H. Min, A. Nathan, S. Sherman, M.
Stewart, and S. Theiss, this conference.
[2] M.D. Jacunski, M.S. Shur, T. Ytterdal, A.A. Owusu, and M. Hack, Mat. Res. Soc. Proc., 424,
213 (1996).
[3] K. Lee, M. Shur, T.A. Fjeldly, and T. Ytterdal, Semiconductor Device Modeling for VLSI
(Prentice Hall, Englewood Cliffs, NJ, 1993), p. 309.
[4] Shaw, J. G., and M. Hack, J. Appl. Phys., 64 (9), 4562 (1988).
[5] M.J. Jacunski, Ph.D. Dissertation, University of Virginia, Charlottesville, VA (1996).
[6] Greve D. and V. Hay, J. Appl. Phys., 61, 1176 (1987).
[7] BSIM3v3 Manual, University of California (1995).
[8] K. Lee, M. Shur, T.A. Fjeldly, and T. Ytterdal, Semiconductor Device Modeling for VLSI
(Prentice Hall, Englewood Cliffs, NJ, 1993), p. 302.
[9] H.C. Slade, Ph.D. Dissertation, University of Virginia, Charlottesville, VA (1997).
[10] http://www.aimspice.con/

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