2.

Resistors, Capacitors, Switches

Analog Design for CMOS VLSI Systems

Franco Maloberti
 Integrated resistors
A resistor is a strip of resistive layer.
L
R = 2Rcont + R
W
Sheet Temperature Voltage
Type of layer Accuracy
resistance coefficient coefficient
Ω/ % ppm/°C ppm/V
€
n+ diff 30-50 20-40 200-1K 50-300
p+ diff 50-150 20-40 200-1K 50-300
n-well 2K-4K 15-30 5K 10K
p-well 3K-6K 15-30 5K 10K
pinched n-well 6K-10K 25-40 10K 20K
pinched p-well 9K-13K 25-40 10K 20K
poly 1 20-40 25-40 500-1500 20-200
poly 2 15-40 25-40 500-1500 20-200

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 1
 Types of resistances

a) diffused resistance

b) diffused resistance into

well

c) n-well (or p-well)

resistance

d) pinched n-well
(or p-well) resistance

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 2
 e) first polysilicon
resistance

f) first polysilicon
resistance with a well
shielding

g) second polysilicon
resistance

h) second polysilicon
resistance with a well
shielding

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 3
 In order to have large value resistors:
 use of long strips (large L/W)
 use of layers with high sheet resistance (bad
performances)
Layout:
rectangular "serpentine".

L L ρ
R= R =
W W xj

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 4
 If the parameters are statistically independent, the standard
deviation of the resistance is:
2 2 2 2 2
 ΔR   ΔL   ΔW   Δρ   Δx j 
  =  +  +   +  
 R   L   W   ρ   xj 
 ΔL   ΔW 
L >> W   <<  
 L W 
€Δρ  is larger for polysilicon resistors than for diffused resistors
  (polysilicon is composed of a conglomerate of independently
 ρ  oriented grain of crystalline silicon)
Accuracy: €
 Absolute accuracy is poor because of the large parameter
drift.
 Ratio (or matching) accuracy is better because it depends
on the local variation of parameters.
Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches
Franco Maloberti 5
 Factors affecting accuracy

 Δρ   Δx   ΔL   ΔW 
   j   ;  
 ρ   xj   L W 

 Polysilicon grain  Implant dose  Etching

size  Side diffusivity  Boundary
€  Crystal defects €  Deposition rate
€  Side diffusivity
 Doping dose
 Stress
 Temperature

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 6
 Stress:
Plastic packages cause a large pressure on the die (≈ 800
atm). It determines a variation of the resistivity.
For <100> material the variation is anisotropic, so the
minimum is with a 45° orientation.
Temperature:
Temperature gradient on the chip may produce thermal
induced mismatch.

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 7
 Etching:
Wet etching: isotropic (undercut effect)
HF for SiO2 ; H3PO4 for Al
∆x for polysilicon may be 0.75-1 µm with standard deviation
0.1 µm.
Reactive ion etching (R.I.E.)(plasma etching associated to
"bombardment"): anisotropic.
∆x for polysilicon is 0.4 µm with standard deviation 0.03 µm
Boundary:
The etching depends on the boundary conditions
 use of dummy strips

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 8
 Side diffusion effect: Contribution of endings

Interdigitized structure

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 9
 Resistor guidelines
For matching:
 Use of equal structures
 Not too narrow (W ≈ 10µm)
 Interdigitize
 Thermal effect compensation
 45° orientation (if stressed)
For good TC:
 Use of n+ or p+ layers
 Use of poly layers
For absolute value:
 Use of diffused layers
 Suitable endings
Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches
Franco Maloberti 10
 Types of integrated capacitors

Electrodes: metal; polysilicon; diffusion

Insulator: silicon oxide; polysilicon oxide; CVD oxide
ε0εr
C= WL
tox
 ΔC 2  ΔL 2  ΔW 2  Δε 2  Δt 2
  =  +  +  r  +  ox 
 C   L   W   εr   tox 
€
Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches
Franco Maloberti 11

€
 Factors affecting accuracy

 Δε   Δt   ΔL   ΔW 
 r  ox   ;  
 εr   tox   L W 

 Oxide damage  Grow rate  Etching

 Impurities  Poly grain size  Alignment
€ Bias condition € €
 Bias history (for
CVD)
 Stress
 Temperature

Absolute accuracy: Better than resistors. The capacitance

value does not depend on doping and diffusion.

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

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 The layout of a capacitor depends on the layers used
to realize the two plates.

To achieve good matching:

 Use of unity capacitors connected in parallel.
 Use W = L fairly large.

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 13
 Common centroid structures

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 14
 Matching accuracy is better than matched resistors,
because:
Δεr Δρ  ΔW   ΔW  (capacitors are
<<   < 
εr ρ  W cap  W res square)
Δtox Δx j
<
tox xj
€
Undercut effect:
W' = W - 2 ∆x L' = L - 2 ∆x
Effective area:
A' = W'L' = WL - 2(L + W) ∆x = A - P ∆x
The undercut effect gives the same proportional reduction if
the perimeter-area ratio is kept constant.
Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches
Franco Maloberti 15
 MOS capacitors features
Temperature Voltage
Type tox Accuracy
coefficient coefficient
nm % ppm/°C ppm/V
poly-diff 6-20 7-14 20-50 60-300
poly1-poly2 8-25 6-12 20-50 40-200
metal-poly 500-700 6-12 50-100 40-200
metal-diff 1200-1400 6-12 50-100 60-300
metal1-metal2 800-1200 6-12 50-100 40-200

Parasitic capacitances:
poly-poly or
diffusion
poly-metal
Cp,b 0.1 C 0.01 C
Cp,t 0.01 C 0.001 C

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 16
 Analog switches
The MOS transistor is a good
switch if it is used to switch
charge (if used to switch current
gives an offset between input
and output).

In the ON-state, after a transient Vout = Vin, hence VDS = 0. The MOS
is in the linear region; its ON-resistance is:
1 1
Ron = =
gds W
µCox(L
)
VGS −VTh
The value of the ON-resistance depends on the overdrive voltage,
Vov = VGS - VTh and on the aspect ratio, through the transconductance
parameter µCox.
€
Modern technologies (3.3 or 2;4 V), minimum area switch (W/L) = 1
with 1V as overdrive displays: Ron,n ≈ 8.6 kΩ Ron,p ≈ 26.3 kΩ.

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 17
 Example
Let us assume that the switch is driven by a 2 MHz clock, stays on for
250 ns, and the load capacitor is 2 pF (rather large for integrated
application). The resulting RC time constant is 17.2 ns for the n-type
and 52.6 ns and p-type transistor, equivalent to 14.5 and 4.75 time
constants. Assuming an exponential response (neglecting any
operation in the saturation region) the output voltage reaches
0.9999995 and 0.991 of the final voltage respectively. The former result
is good enough for any analog applications, the latter one corresponds
to an error of 1% witch is not acceptable for high precision.
Conclusion:
 A minimum area n-channel switch is capable of driving 2 pF, running
at a few MHz clock.
 A minimum area p-channel switch is capable of driving 2 pF with a
clock control not exceeding 1 MHz.

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 18
 The complementary switch transistor is the parallel of an n-
channel and p-channel transistor.
Its ON-conductance is:

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 19
 Clock feedthrough

In the ON-state
(VG – Vin) > VTh
The charge stored on the channel
Qch = W L Cox (VG – Vin – VTh)
at the time toff the charge Qch disappears.

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 20
  The charge Qch injected partially on the source and partially on the
drain.
 We can assume that a fraction a of the charge from the channel
affects the output node and is integrated on the store capacitor.
Similarly, we analyze the charge injected from overlap capacitance.
 When the channel is still existent, the low impedance node pulls part
of the charge: we assume that a fraction β, remains in the storing
capacitor.
 After toff, we have no interacting injections on the two sides.
 The total charge that remains in the storing capacitor is:

 WxovCoxC1  WxovCoxC1
[ ( )]
Qinj = α WLeff Cox VDD −Vin −VTh + β 
WxovCox + C1
(VDD −Vin −VTh )
+
 WxovCox + C1
(
Vin + VTh )

The charge, divided by the stored capacitor, gives the voltage error
€
produced by clock feedthrough.

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 21
 Clock feedthrough cancellation

 Dummy switch
 Two complementary switch delayed driving
 Complementary switches
 Compensation scheme
 Fully differential structure
 Dummy switch:

(WL)1 = 2(WL)2
W1 = 2 W2

 M2 must close after the

opening of M1
Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches
Franco Maloberti 22
 Two switches:
If a switch with non-
minimum area must
be used

Complementary
switches:
Effective only if Vin =
constant (virtual
ground)

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 23
 Compensation scheme:

Fully differential structure:

The injected charge is
equivalent to a common
mode signal (rejected by the
CMRR).

Analog Design for CMOS VLSI Systems 2. Resistors, Capacitors, Switches

Franco Maloberti 24