Tim Wang Lee 2018.10.

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Keysight EEsof Signal Integrity Application Scientist
Transmitter Receiver

Channel

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CPU Graphic card Cable On board video processor LED display

Interconnects

Signal integrity is about the problems interconnects

introduce and how to avoid them.
– Dr. Eric Bogatin
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The case of the failing virtual channel

1 Simulate the channel

Find the root cause of

2 degradation

3 Explore design solutions

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 Eye diagram Mixed-mode S-parameters

Time domain reflectometry Single pulse response

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8 Lanes PCIe Express with Tx Rx Equalization IBIS-AMI Back Channel Interface

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The case of the failing virtual channel

1 Simulate the channel

Find the root cause of

2 degradation

3 Explore design solutions

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1
Channel
0
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PRBS: Pseudo-Random Binary Sequence
By sending PRBS, we are testing how the channel affects all the possible transmitted data pattern.
PRBSX: The 2x-1 pseudo-random binary sequence combines every permutation of x bits.

1 0 1 1 1 1 0 0 1 1 0 1 1 1 0 1 1 1 0 0 1 0 1 0 1 0 0 1 0 1

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2UI 2UI 2UI

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11
PRBS at the transmitter Received PRBS at Receiver

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The case of the failing virtual channel

1 Simulate the channel

Find the root cause of

2 degradation

3 Explore design solutions

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 S21 (Port 2 excited by port 1)
• Transmission coefficient
Freq = f0
• Insertion loss
Port 1 Port 2
Channel

Signal Integrity Convention:

RL (dB)  20log S11
S11 (Port 1 excited by port 1)
• Reflection coefficient
• Return loss
IL (dB)  20log S21
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 Port 1 Port 2

Transmission line
Differential
Port 1
Mixed-mode Differential
Port 2

Vindiff S-parameters
Transmission line Voutdiff
Vincomm Port 3 Port 4 Voutcomm

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Smixed-mode  Differential Signal
Stimulus
Common Signal
Stimulus

Differential
S DD11 S DD12 S DC11 S DC12
Response
S DD 21 S DD 22 S DC 21 S DC 22
Common
SCD11 SCD12 SCC11 SCC12
Response
SCD 21 SCD 22 SCC 21 SCC 22
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S DD11 Differential response at port 1, excited
by Differential input at port 1.

S DD11 Related to differential return loss.

S DD 21 Related to differential insertion loss.
SCD 21 Mode-conversion: EM generation.
S DC 21 Mode-conversion: EM susceptibility.
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 Expectation Expectation

SDD11 (dB)
? SDD21 (dB)
?
Freq (GHz) Freq (GHz)

3-inch 3-inch
Structure Via
microstrip stripline
Estimated Loss
(dB at Nyquist)
Impedance
(Ohm)
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3-inch microstrip differential pair

Differential Via structure

3-inch stripline differential pair

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 14 mil 42 mil 14 mil

Single-ended Microstrip Impedance Because of solder mask, we expect:

Rule of Thumb: W/H = 2  Z = 50 Ohm differential impedance <100 Ohm

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 8 mil 24 mil 8 mil

Single-ended Microstrip Impedance

Rule of Thumb: We expect:
0.8 < W/H < 1  Z ~ 50 Ohm differential impedance ~100 Ohm

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 3-inch 3-inch
Structure Via
microstrip stripline
Estimated Loss
(dB at Nyquist)
Impedance
<100 ~100
(Ohm)
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 Date Rate: 32 Gbps
Nyquist Frequency: 16 GHz
Estimated Loss: ~ 0.1 dB/in/GHz

3-inch 3-inch
Structure Via
microstrip stripline
Estimated Loss
(dB at Nyquist)
Impedance
<100 ~100
(Ohm)
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 Date Rate: 32 Gbps
Nyquist Frequency: 16 GHz
Estimated Loss: ~ 0.1 dB/in/GHz

3-inch 3-inch
Structure Via
microstrip stripline
Estimated Loss
5 dB 5 dB
(dB at Nyquist)
Impedance
<100 ~100
(Ohm)
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 Date Rate: 32 Gbps
Nyquist Frequency: 16 GHz
Estimated Loss: ~ 0.1 dB/in/GHz

3-inch 3-inch
Structure Via
microstrip stripline
Estimated Loss
5 dB small 5 dB
(dB at Nyquist)
Impedance
(Ohm)
<100 ? ~100

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 Expectation Expectation

SDD11 (dB) - 30 dB
SDD21 (dB)
-10 dB at 16 GHz

Freq (GHz)
Freq (GHz)

3-inch 3-inch
Structure Via
microstrip stripline

Estimated Loss
5 Small 5
(dB at Nyquist)
Impedance
(Ohm)
<100 ? ~100

Not what we expect!

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 microstrip differential pair
3-inch 3-inch
Structure Via
microstrip stripline
Differential Via structure Estimated Loss
5 Small 5
(dB at Nyquist)
stripline differential pair

Transmission line only

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 Data rate: 32 Gbps
Nyquist: 16 GHz
Bandwidth: 5*16 = 80 GHz
Wavelength: 6 in/nsec/80 ~ 75 mil

75 mil
~75 mil

Transmission line:
Voltages and currents vary
in magnitude and phase
over physical length.
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 Top View

 : Reflection Coefficient
Z 2  Z1

Z1 = 50
Z1  Z 2

Z2
Z2
Z2 short Z2 < 50 Z2 = 50 Z2 >50 Z2 open
(Ohm)

Γ -1 -1<Γ<0 0 0>Γ>1 1

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Top View

Transmission line stub

Open
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Top View
V

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 V


Len 
4 
Delay 
V 2

 1
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 V


Len 
4
Quarter-wave stub resonance
At frequency where the physical length if the
stub is a quarter of a wave length, it seems like
nothing is being transmitted (virtual short).
 1
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  v v in
len     4  len f res   v 6
4  4  len nsec
1.5
f res (GHz)  For FR4, expect fres = 20 GHz
Len ~ 75 mil
len (in)

Len ~ 75 mil

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3-inch microstrip differential pair

Differential Via structure

3-inch stripline differential pair

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 1  (t ) Vreflected (t )
Z DUT (t )  Z 0 (t ) 
1  (t ) Vincident (t )

Vincident
Step
Channel Open
Generator

Reflection
Vreflected
Monitor
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 Open

Estimated Delay (FR4): 6 in/nsec

3-inch 3-inch
Structure Via
microstrip stripline
Round Trip Delay
(nsec)
Small
Impedance
(Ohm)
<100 ? ~100
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 Open
100 Ohm ~100 Ohm ~100 Ohm

100 Ohm ?
Open

Estimated Delay (FR4): 6 in/nsec 0.5 nsec 1.5 nsec 1.6 nsec 2.6 nsec

3-inch 3-inch
Structure Via
microstrip stripline
Round Trip Delay
(nsec)
1 Small 1
Impedance
(Ohm)
<100 ? ~100
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 Zdiffvia
Assume 100 Ohms

ZdiffStriplineFeed

Zstub Parallel combination

is about 50 Ohms.

Assume 100 Ohms

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40
The Root Cause:
The via stub is resonating at frequency
close to Nyquist and degrading the
frequency spectrum of the input signal.

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The case of the failing virtual channel

1 Simulate the channel

Find the root cause of

2 degradation

3 Explore design solutions

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Expect eye to be more open.

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 Decision Feedback

+ Equalization

But… How many taps?

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 Single pulse Single pulse response

Channel

• Rise Time
• Data rate (Unit Interval)

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 Cursor
Decision Feedback Equalization

Symbol
+ Detector
Post-cursor
Pre-cursor Feedback
Decision
Algorithm

One Unit Interval (UI) If I detect a “1”,

emphasize the next “0”.

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If I detect a “1”,
emphasize the next “0”.

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 Decision Feedback

+ Equalization

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49
 Decision Feedback

+ Equalization

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52
8 Lanes PCIe Express with Tx Rx Equalization

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Control-Impedance Line Designer quickly optimizes for Zdiff.

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Via Designer solves with
3D-full wave engine.

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Data Transfer: 8 GT/s
0.1 dB/In/GHz at fNyquist=4 GHz

8 dB attenuation

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0.1 dB/In/GHz at fNyquist=4 GHz
8 dB attenuation

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58
 Decision Feedback

+ Equalization

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 Tx EQ Channel Rx EQ
RX EQ
Tx EQ
Baseboard Controls Add-in Card
Controls
• FFE
• FIR Taps
• DFE
• Preshoot
• CTLE

Auto-Negotiation

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Before Auto-Negotiation After Auto-Negotiation

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The case of the failing virtual channel

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YouTube Video:
https://youtu.be/mpyMWuVrKKc
Workspace Download:
http://www.keysight.com/find/eesof-how-to-solve-si-problems
Tim’s Knowledge Center:
http://edadocs.software.keysight.com/display/TKC/20181025+SI+Journal+Signal+Integrity+Webinar

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