Methodology for Low Power Test Pattern Generation

Using Activity Threshold Control Logic

Srivaths Ravi, V. R. Devanathan, and Rubin Parekhji
Texas Instruments (India) Pvt. Ltd.
Bangalore, India 560 093
srivaths.ravi,vrd,parekhji
@ti.com

Abstract— This paper proposes a new technique of power-aware repeat fill, preferred fill, and so on. Some of these fill options do not
test pattern generation, wherein the test mode power constraints are require any modification of the ATPG tools, and are also available in
specified using pseudo hardware logic functions (referred to as power
commercial tools. X-fill techniques are highly effective in reducing
constraint circuits) that augment the target circuit fed to the ATPG
tool. The novelty of this approach is three-fold: (i) The ATPG tool the power consumption of raw ATPG patterns, but are less effective
only sees the enhanced circuit. This influences the generation of the in the case of compressed and/or compacted patterns (as we will also
test cubes themselves, as against post-processing of these cubes for a see later in the paper).
given pattern. (ii) Pattern generation can be driven to minimize test If the ATPG algorithm can be modified, low power patterns can be
power according to a programmable switching activity threshold, and
hence, is scalable. (iii) The same constraint circuit can also be effectively generated during the course of test generation, rather than resorting to
used for pattern filtering to isolate patterns which cause high switching fill-based solutions. For example, the techniques in [12] use power-
activity. Additionally, the proposed method does not require any changes aware cost functions that minimize weighted transition counts during
to the pattern generation tool or process. This paper describes the the process of test pattern generation.
methodology, together with techniques for realizing the hardware circuit
and specifying thresholds. Experimental results on various benchmark
circuits (including an industrial design) are presented to show the B. Paper Overview and Contributions
effectiveness of this approach.
In this paper, we tackle the problem of generating power-aware
I. I NTRODUCTION patterns for scan-based circuits using off-the-shelf commercial ATPG
tools. Our only requirement is that the ATPG tool should be in-
Test power concerns are today coming to the forefront of chips herently capable of accepting constraints in some form that can be
designed in deep sub-micron technologies. It has been observed effective during various scan test phases (e.g., shift, capture).
that the power consumed during test is several times higher than
Our solution is motivated by a simple observation that the problem
functional power consumption [1], [2] making test power a deciding
of generating power-aware patterns can be viewed as a constrained
factor for diverse aspects such as power grid design, packaging, and
ATPG problem. We recognize that power constraints are typically
even tester choice [3]. Increase in test power is largely determined
mathematical computations operating on the dynamic state of the
by the operating frequency used during test, the amount of logic
circuit, and thus, they can be easily modeled in hardware as virtual
concurrently excited, and the process, temperature and voltage (PTV)
constraint circuits added to the target circuit. The enhanced circuit,
corners at which the tests are performed.
composed of the device-under-test and power constraint circuit, forms
Another cause for concern is that the increased switching activity
the input to the ATPG tool, forcing ATPG to generate only those
during test can result in significant IR drop [4] that can cause normal
patterns that satisfy the modeled constraints. Thus, no modifications
chips to be classified as fails, resulting in low yields. Technology scal-
are required of the ATPG tool.
ing, stringent customer power consumption requirements for battery-
We analyze the challenges involved in using this novel approach
operated appliances such as cell-phones and portable media players,
for low power pattern generation, and suggest solutions that make
field testing needs in automotive electronics, etc. are tightening the
it practically usable with commercial ATPG tools. We demonstrate
bounds on allowed test power. These trends are forcing test engineers
applications of the proposed framework in filtering patterns that
to develop innovative DFT architectures to reduce power and/or
do not meet the specified constraints (low power pattern selection)
low power test pattern generation flows. Low power ATPG patterns
and also finding new patterns that meet the specified constraints
are attractive because they require no inherent modifications of the
(low power pattern generation). Our experiments in the context
design. Our work deals with the problem of generating low power
of a commercial ATPG tool with standard benchmarks as well as
test patterns with no modifications required of the ATPG tool.
an industrial design show that the proposed approach facilitates a
A. Related Work scalable reduction of switching activity using user-controllable limits
on pattern/response toggle count. When this threshold was specified
Low power ATPG techniques can be used to create patterns that
as 50% of the total number of sequential cells, the proposed flow
are optimized to achieve minimum switching. A popular way to do
was able to generate test patterns (responses) with toggle counts not
low power ATPG today is through “intelligent don’t care bit filling”
achievable by adjacent fill based methods with small overheads in
or constant (constrained) fill techniques [4]–[10]. The number of
test data volume (1.5% to 43.2%).
care bits in uncompressed or uncompacted test patterns is usually
a small fraction of the total number of bits [5]. As a consequence,
II. M OTIVATION
judicious filling of the don’t-care (or X) bits to reduce toggling during
shift and/or capture can achieve reduction in power consumption In this section, we use illustrative examples to highlight the limita-
(average/peak). Examples of X-fill techniques include zero-fill (filling tions of low power ATPG techniques such as constrained (constant)
X bits with 0), adjacent fill (filling X bits with the nearest care bit), fill techniques, especially in the presence of compression.
 10
9
20
Number of Patterns Random Fill Random Fill 0-Fill
8 1-Fill

Dynamic Power
Adj-Fill
7
Adjacent Fill 15

(milliWatts)
12% 1-fill Adj-Fill
6 Random Fill 0-Fill
5 10
4 Peak
3 Toggle 5
2
1
0
0 First 5 patterns Last 5 patterns
0.44 0.54 0.64 0.74 0.84 0.94
Normalized Toggles Fig. 3. Impact of X-fill techniques on compacted test patterns

Fig. 1. Toggle histogram profile for s1423 Design A Design B

10.7 325
10
9 Random Fill 10.6 324

Power (mW)

Power (mW)
Design A

Design B
Number of Patterns

8 Adjacent Fill 0.9% 323

10.5
7 322
6 10.4
80% of Peak 321
5
10.3 320
4
3 10.2 319
2 Random Fill Adjacent Fill Zero Fill
1
0 Low-Power Fill Techniques
0.44 0.54 0.64 0.74 0.84 0.94

Normalized Toggles Fig. 4. Impact of X-fill techniques on compressed and compacted patterns

Fig. 2. Toggle histogram profile for s1423 corresponding to power

constrained patterns
Our first example studies the toggle profiles of patterns generated
by a commercial ATPG tool using various X-fill schemes, and
shows that alternative toggle profiles with significantly reduced toggle
counts can be generated by the same ATPG tool using our proposed
approach, with very little overhead in test data volume.
Example 1: Figure 1 shows the toggle histogram profiles for random
and adjacent fill pattern sets generated by a commercial ATPG tool
for the ISCAS benchmark circuit s1423 for a launch-off-shift (LOS)
fault model. The 74 scan flip-flops in the circuit were organized into
a single scan chain. We can see that both the distributions have a
tail, which corresponds to the patterns having high toggle counts. As
expected, adjacent fill patterns have a shorter tail when compared
with random fill.
However, it turns out that we can achieve a significantly better
toggle distribution by using our proposed framework, which uses the
same ATPG tool. Figure 2 shows the toggle histogram profiles that are
generated subject to a reduced toggle or activity threshold (specified
to be 80% of the original peak toggle value shown in Figure 1). We
achieve the same fault coverage as in the former scenario, with a
small increase in pattern count (10% for adjacent fill).  fill techniques (in commercial ATPG tools) can operate only on the
The following examples consider the use of compaction and
compression in various example designs, and shows the inability
of fill techniques available in commercial ATPG tools to provide
significant power savings.
Example 2: We considered compacted patterns of a module T from
an industrial circuit that uses full scan. Module T includes 6292
sequential and 24350 combinational cells. We studied the effect of
using various fill options available in a commercial ATPG tool on the
dynamic power consumption of this circuit. Power consumption data
was obtained for the first and last five patterns in the stuck-at pattern
set using the gate-level power estimation tool PrimePower [13].
The results are presented in Figure 3. We can see that low power
fill techniques can achieve only 12% power reduction for the first
five patterns, while having little effect on the last few patterns.

Example 3: We next considered two designs that included a combina-
tional decompressor and compactor to support test data compression
– Design A has 7728 sequential and 60500 combinational cells ,
while Design B has 113666 sequential and 646164 combinational
cells. For the compressed and compacted patterns, we studied how
fill techniques available in a commercial ATPG tool can help lower
the circuit’s dynamic power consumption. Figure 4 shows that fill
techniques have little impact towards reducing the switching power.
In Design A, neither zero nor adjacent fill techniques reduce the power
consumption (random fill results in the lowest power consumption),
while in Design B, zero fill results in lowering the power consumption
by just 0.9%. 
The reason for the poor performance of the fill techniques in the
above designs is that in a compression environment, the bit utilization
is increased by driving multiple scan chains simultaneously. As
a result, the care bit utilization is increased. At the same time,
controllability over don’t care bits is reduced and this restricts the
X-bits that remain to be filled.
Even in the absence of compression/compaction, we observe that
test cubes determined by the ATPG tool (as against creation of test
cubes which are fill friendly). Thus, fill techniques can, at best, play
only a post-processing role in ATPG flows today. This implies that
only a portion of the pattern space can be explored from a power
consumption standpoint, resulting in marginal power savings.
III. P ROPOSED F RAMEWORK
This section discusses various aspects of the proposed framework.
A. Basic Concepts: Power Constraint Circuit
We observe that the problem of generating power-aware patterns
can be viewed as a constrained ATPG problem. Examples of con-
straints imposed by these patterns include: (i) A bound on the toggle
 POWER
THRESHOLD INPUTS
adder tree

SF1
+ Monitored
SF2 Signals
Power
Target
transition Constraint
SF3 Circuit
count Circuit

+ + tc_out
<=

+ Meet Constraint
OUTPUTS
(Y/N)?
SFN
τ Fig. 6. Enhanced netlist embedding a power-constrained circuit
Transition Counter

90
Fig. 5. An example implementation of a power constraint circuit 80
70

Fault Coverage (%)

60
count is satisfied by the nodes in the circuit, (ii) One portion of the 50
circuit has lesser switching than others, and so on. We further observe 40
30
that these power constraints are simple mathematical computations. 20
Hence, they can be easily encapsulated as a circuit (called power 10
constraint circuit or PCC), as illustrated below. 0

Unconstrained

Adder based
Example 3: Consider a circuit with scan flip flops (  

 )

Partitioning

Filter + LUT

Partitioning
Comparator

based PCC
LUT based
based PCC

PCC with
Adder +

with
PCC
ATPG
undergoing a scan shift operation at time instant  . We can count
the number of transitions due to the scanning out of values in the
flops ( 
) at time  due to the shift operation at time 
using the following equation. Fig. 7. Fault coverage recovery using various strategies
   

    ! 
In the above equation,   denotes the value
at time  in flop
 . Since the transition count T is proportional to the switching
power of the flip-flops, one example power constraint would be to
limit the transition count during shift, and hence, control the power
consumed during shift. For example, the following equation limits
the shift power to be lesser than a user-specified threshold " .
 #
" (2)
It is easy to see that this power constraint (Equation 2) can be
represented as a circuit, whose inputs are the outputs of the scan flip-
flops, and the output is constrained to the specified threshold. One
possible implementation for the power constraint circuit (PCC) can
be by simply using XOR gates, adders, and a comparator. Figure 5
shows the corresponding block diagram.
B. A Simple Flow for PCC Based Low Power Pattern Generation
Figure 6 is a generalized depiction of how the PCC is used in
tandem with a target circuit. The inputs to the PCC are the signals
being monitored, and an input threshold. The combined entity is
referred to as an enhanced netlist, which works as follows. If a
stimulus is applied at the inputs of the target circuit, the PCC
functions as a runtime monitor and checks if the monitored signals
meet the power threshold according to the mathematical equation
represented by the PCC. The output of the PCC indicates the result
of this check.
Low power ATPG can now be performed as follows. Since we
desire only those test patterns to be generated that meet the constraints
encapsulated in the PCC, we can simply constrain the output of the
PCC to be a fixed value (say, ’1’ for the PCC shown in Figure 6)
and feed the enhanced netlist to the ATPG tool. The ATPG tool is
thus co-erced to generate only those patterns that meet the constraints
imposed by the embedded PCC.
(1)
C. PCC Implementation
We used the adder  comparator based implementation of the PCC
with various circuits, and found that the fault coverage achieved by
the ATPG tool in the presence of constraints was inadequate. Figure 7
presents the data for one example circuit s13207. Bars 1 and 2 show
the gap in fault coverages between the unconstrained and constrained
(using the basic PCC implementation) scenarios. We then studied
various ways of implementing the PCC so as to improve the ATPG
tool’s performance. These include
$ Implicit comparison by removing the comparator from the PCC
and placement of 0/1 constraints on the multi-bit output of the
adder tree in the PCC.
$ Use of partitioned PCC design to present a more tractable
implementation to the ATPG tool. The basic idea here is to
break the scan chain into multiple disjoint partitions, with a
PCC instantiated for each partition. Since each PCC is now
independently responsible for a reduced set of the flops, the
PCC implementation becomes much simpler.
$ Alternative implementation of PCC using a lookup table (LUT)
approach, wherein the table can contain the list of violating
patterns or its signatures. Constraints are introduced into the
ATPG tool such that the patterns generated are not present in
the table of violating patterns.
Figure 7 tracks the effect of the above enhancements to the PCC
implementation. First, we observed that the performance of adder
based PCC implementations has not improved when just the com-
parator is removed. (i.e., fault coverage bars 2 and 3 of Figure 7
differ only by 7%). On the other hand, the lookup table based PCC
(Bar 4) results in considerable fault coverage improvement (69.3%).
However, this number is still lesser than the unconstrained coverage
number (82.1%).
In order to recover the original fault coverage, we decided to adopt
a two-phased strategy for the ATPG tool to handle the complexity of
constrained test generation.
 activity threshold. Column 5 reports the additional patterns generated
Perform unconstrained
ATPG with by the proposed pattern generation flow, while Column 6 indicates
PCC logic no-faulted
Target
3
the total number of power-constrained patterns. Column 7 reports
Circuit
Test the final fault coverage. The results show that the power-constrained
Patterns
patterns are able to achieve very close to the original fault coverage,
Activity
Threshold Apply constraint checks Discarded
with increase in test patterns ranging from 1.5% to 43.2%.
Generate Power Constraint using ATPG tool during violating
Circuit (PCC) using a partitioned fault simulation patterns
List of
and LUT based architecture 1
4 TABLE I
Monitored
Signals Good PCC- BASED ATPG ON E XAMPLE C IRCUITS
PCC PCC I/O Patterns
Constraints
Orig. Pattern Count Final
Integrate with Target
Identify faults not
detected by the good Cov Orig Viol Addn Final Coverage
Circuit 2
patterns
5 s1423 94.70% 70 6 13 77 94.37%
Perform constrained ATPG
s5378 68.04% 128 6 8 130 67.97%
Enhanced
to generate power -
constrained patterns
s9234 89.03% 243 4 9 248 88.90%
netlist 6
s13207 82.14% 251 5 30 276 82.00%
Power- s15850 86.18% 168 6 27 189 86.18%
constrained
patterns s38417 97.03% 298 4 28 322 96.88%
s38584 86.31% 194 4 88 278 86.07%
Design A 99.81% 322 118 153 357 99.79%
Fig. 8. Proposed flow for generating low power test patterns

$ V. C ONCLUSIONS
In the first phase, we generate ATPG patterns in an uncon-
strained manner and then use the PCC to filter the patterns that
do not satisfy the specified activity threshold.
$ In the second phase, we perform constrained test generation
targeting only those faults which are not covered by the good
patterns.
In this way, we get the ATPG tool to perform constrained ATPG for
only a reduced set of faults. Bar 5 of Figure 7 shows that we are
able to recover the lost fault coverage by using this approach.
D. Final Flow Overview
Figure 8 shows the final flow that incorporates the various opti-
mizations described in Section III-C. In Step 1, we use a partitioned
and look-up table based architecture for the design of the optimized
PCC. This step also outputs the constraints on the PCC’s I/Os that
need to be considered during ATPG. The PCC thus generated can
be hooked up with the target circuit to generate the enhanced netlist
(Step 2).
Steps 3-6 capture the two-phased ATPG flow that evolved out of
the discussion in Section III-C. In Steps 3 and 4, we generate ATPG
patterns in an unconstrained manner using available low power fill
techniques (e.g., adjacent fill) and then exploit the constraints on the
PCC I/Os to filter the patterns during fault simulation (all patterns that
do not satisfy the specified activity threshold are dropped). In Steps
5 and 6, we perform constrained test generation targeting only those
faults which are not covered by the good patterns (PCC faults are
no-faulted here as well). In this way, we augment the good pattern set
with a minimum set of patterns to form the final power-constrained
pattern set.
IV. E XPERIMENTS AND R ESULTS
We implemented the proposed framework described in Section III
using the commercial ATPG tool TetraMAX [11] and various scripts.
The evaluation was performed on various ISCAS benchmark circuits
and also on an industrial circuit that supports test data compression
(Design A of Section II). Table I reports the results for LOS
pattern sets. The toggle threshold was set to 50% of the number
of sequential cells. Column 2 shows the original fault coverage of
patterns from using an adjacent fill based ATPG run. Column 3
reports the corresponding pattern count, while Column 4 reports the
number of patterns in that pattern set that do not meet the specified
This paper presents a new framework for reducing test power
through generation of directed test patterns using commercial ATPG
tools. The framework simply represents power constraints during test
operations as constrained hardware functions that can be added to
the netlist during ATPG. Thus, ATPG tools can be forced to generate
patterns that meet the specified power constraints. Experiments are
performed on various circuits using the proposed flow. The results
show that such a framework is more effective in generating low power
test patterns than conventional fill based techniques.
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