module parking_plaza(clock,reset,slots,pins,ent,ext,state, notavail);

input clock,reset;

input ent;
input ext;
output reg [3:0]slots;
input [1:0] pins;
reg [1:0] inid;
output reg [2:0] state;
reg [2:0] next;
parameter idle=3'd0,
tabl=3'd1,
entering =3'd2,
checkempty=3'd3,
exiting =3'd4;
//control signals
reg clear_reg;
reg clear_slot;
reg load_inp;
reg enter_slot;
output reg notavail;

always @(posedge clock)

if(reset)
state<=idle;
else
state<=next;
//state transitions
always @(state, ent, ext)
begin
case(state)
idle:
next=tabl;
tabl:
begin if (ent) next=entering; else if(ext) next=exiting; e
lse next=tabl; end
entering:
begin next=checkempty; end
checkempty:
begin next=tabl; end
exiting:
begin next=tabl; end
endcase
end
//control unit
always @(state, ent, ext)
begin
case(state)
idle:
begin clear_reg=1;
load_inp=0;
enter_slot=0;
 clear_slot=0; end
tabl:
begin clear_reg=0;
enter_slot=0;
clear_slot=0;
load_inp=0;

end
entering:
begin
load_inp=1;
clear_slot=0;
enter_slot=0;
clear_reg=0;
notavail=0;
end
checkempty:
begin
load_inp=0;
if(~slots[inid])
enter_slot=1;
else
begin
enter_slot=0;
notavail=1;
end
clear_slot=0;
clear_reg=0;
end
exiting:
begin
enter_slot=0;
load_inp=1;
clear_slot=1;
clear_reg=0;
end
endcase
end
//datapath unit
always @(posedge clock)
begin
if(clear_reg)
slots<=0;
if(load_inp)
inid<=pins;
if(enter_slot)
slots[inid]<=1;
if(clear_slot)
slots[inid]<=0;
end
endmodule