Sheet

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CMOS Logic

In many aspects of RF design it is useful to have some knowledge of logic design, in

particular PLL systems always employ some form of phase detector and sometimes a
prescalar/divider.

First lets re-cap on the operation of a N-type CMOS switch.

Figure 1 shows the switch OFF condition ie no current flow between the drain and source.
The bulk or substrate is made of lightly doped p-type silicon, which consists of positive ‘holes’
(and a few negative electrons). An area of highly doped (many electrons) is deposited on the
substrate in two positions to form the source and drain connections. Bridging these source
and drain terminals is an area of insulating SiO2 (Silicon Dioxide) coated in metal which now
forms the gate terminal.

With no potential on the gate, there is no depletion region for current to flow between the
drain and source terminals and so the switch is off.

Heavily doped
Gate
N-type
Silicon Metal layer
PolySilicate
SiO2 Insulating
0V Layer

Source Drain
- - - - - -
- - - -

+ + + + -
- Heavily doped
+ N-type
+ Silicon
- + + + +
Lightly doped p-type substrate

Figure 1 Showing the CMOS switch in the ‘OFF’ condition, as there is 0V on the gate
junction and there is no conducting layer under the gate to allow current to flow
between the drain and source junctions.

In Figure 2 the ‘ON’ state is shown ie +5V is applied to the gate terminal. In this case the
postive gate potential attracts electrons from the substrate causing a region of electrons
formed under the gate insulation region. Current can now flow through this induced n-channel
‘inversion region’ between the drain and source terminals.
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Gate
Metal layer
PolySilicate
SiO2 Insulating
+5V Layer

Source Drain
- - - - - -
- - - - - - - -

+ + + + -
Current flow -
through the + Electrons attracted
Inversion + to area under the
- + + + + gate
Lightly doped p-type substrate

Figure 2 Showing the CMOS switch in the ‘ON’ condition, as there is +5V on the gate
junction. Electrons from the substrate are attracted to the area under the gate causing
a conducting path between the drain and source junctions.

CMOS INVERTER (NOT Gate)

To form a simple inverter circuit we need to add a load resistor as shown in Figure 3.

Vcc

N-Type CMOS

Vout

Vin

Figure 3 N-type CMOS FET switch with resistive load resistor.

With Vin set to 0V the voltage across the gate to source junction will also be 0V. For a N-Type
CMOS FET to switch the Vgs voltage needs to be > VT+VSAT, so with Vgs set to 0V the switch
will be off and vout will be at Vcc (Vout will be directly connected to Vcc via the resistor R). In
this case vin = lo; Vout = hi.
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When Vin is set to +5V (which is much greater than VT+VSAT) the CMOS Fet will be switched
on and Vout will be shorted to ground making it 0V. In this case vin = hi; Vout = lo.

Note that current will flow through the resistor R when the switch is ON and this is a waste of
power. However, we can use a push-pull configuration using a P-type and N-type CMOS
switch as shown in Figure 4.
Vcc (+5V)

P-Type CMOS
TR1

Vout
Vin

N-Type CMOS
TR2

Figure 4 Push-Pull CMOS Inverter circuit.

With Vin Set to 5V (and Vcc set to 5V).

Vgs across the N-type CMOS FET (TR2) will be 5V, well above VT+VSAT and therefore TR2
will be switched ON.

The Vgs across the P-type CMOS FET (TR1) will be 0V (Vcc (5V) – Vin (5V)). This device
requires VT+VSAT below Vcc before it switches on and so this device is OFF.

With TR1 OFF and TR2 ON - Vout will be connected to 0V via TR2.

With Vin Set to 0V (and Vcc set to 5V).

Vgs across the N-type CMOS FET (TR2) will be 0V, below VT+VSAT and therefore TR2 will be
switched OFF.

The Vgs across the P-type CMOS FET (TR1) will now be ~ -5V (Vin (0V – Vcc (5V)). This
device requires at least VT+VSAT (~1V) below Vcc before it switches on – in this case it will be
nearly 5V and so this device will be switched ON.

With TR1 ON and TR2 OFF - Vout will be connected to 5V (Vcc) via TR1.

Note the Bulk/substrate connections (shown by the RED arrow), N-type bulk is connected to t
he lowest voltage in this case 0V and the P-type connected to the highest voltage in this case
Vcc (+5V).
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The circuit was simulated to verify operation using a 0.8um silicon-gate bulk CMOS n-well
process using ADS.

Figure 5 shows the ADS simulation setup using a Transient (Time domain) simulation with the
inverter circuit connected to a square wave pulse generator operating at 50KHz.

VDD

MOSFET_PMOS
MOSFET2
Model=MOSFETM V_DC
VtPulseDT Length=L um SRC1
SRC2
Width=W um Vdc=5.0 V
Vlow=0 V
DT
Vhigh=5 V Vout
Delay=0 nsec
Width=10 usec
Period=20 usec MOSFET_NMOS
Rout=1 Ohm MOSFET1
Vin Model=MOSFETM
Length=L um
Width=W um
TRANSIENT

Tran
Tran1
LEVEL1_Mode LEVEL1_Mode
StopTime=50 usec
Var
VAR MOSFETM1 MOSFETM2
MaxTimeStep=250 Eqn
VAR1 Vto=0.7 Uo=660 Vto=0.7 Uo=210
LAMBDA=0.1/L Kp=50e-6 Kp=50e-6
L=1 Gamma=0.6 Gamma=0.6
W=1 Phi=0.8 Phi=0.8
Lambda=LAMBDA Lambda=LAMBDA
Pb=0.95 Pb=0.95
Cgso=220e-12 Cgso=220e-12
Cgdo=220e-12 Cgdo=220e-12
Cgbo=700e-12 Cgbo=700e-12
Cj=770e-6 Cj=560e-6
Mj=0.5 Mj=0.5
Cjsw=5e-10 Cjsw=5e-10
Mjsw=0.38 Mjsw=0.35
Tox=140e-10 Tox=150e-10
Ld=0.016 um Ld=0.015 um

Figure 5 ADS simulation setup to analyse the CMOS inverter based on 0.8um gate
process. The pulse source provides a 50KHz square wave to the inverter. Note that the
P-MOS device source is connected to Vcc and the N-MOS device source is connected
to ground (the two drains are connected together to form the output).
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CMOS INVERTER
(0.8um Silicon-gate bulk CMOS n-well process)
6

4
Vin, V

-1
0 10 20 30 40 50

time, usec
6

4
Vout, V

-2
0 10 20 30 40 50

time, usec

Figure 6 Resulting waveforms generated from the ADS simulation shown in figure 5,
showing the inverting action. Note the overshoot appears to be a ‘quirk’ of the
transient simulation.
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CMOS NOR Gate

A NOR gate can be designed by adding CMOS inverters in parallel. Figure 7 shows the circuit
diagrams of a 2 NOR gate if more inputs are required more devices are added in parallel with
TR3/TR4 and is series with TR1/TR2.

Looking at the truth table we can see that a logic high output only occurs when A & B are
low. With A & B at 0V CMOS P-type switches TR1 & TR2 will be ON – connecting Vout to
Vcc. Also the N-type CMOS switches TR3 & TR4 will be switched off (as Vgs =0 which is <
VT+VSAT). In all other cases (where A or B are 1) one of the P –type switches will be OFF
and Vout will not be connected to VCC always resulting in a logic low on the output.

Vcc (+5V)
A B Vout
0 0 1
0 1 0
1 0 0
P-Type CMOS
TR1 & TR2 1 1 0

N-Type CMOS
Vin – ‘A’ TR3 & TR4

Vin – ‘B’
Vout A+B

Figure 7 Two-Input NOR gate. To add more inputs another N-type device is added in
parallel with TR3 & TR4 and another P-type device added in series with TR1 & TR2 –
the gates of the new devices connected together to form the new input.
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CMOS NAND Gate

The structure of a 2-input NAND gate is the inversion of the 2-input NOR gate, ie parallel
devices connected to +5V Vcc and series devices connected to ground as shown in Figure 8.
The main problem with this circuit are the cumulative Vsats of the series devices.

The ADS transient simulation of the NAND is shown in Figure 9 and is used as a basic
building block for other more complex logic circuits eg flip-flops.

The practical limit is for four devices ie 4-input NAND gate, to generate more inputs then
these circuits can be cascaded as shown by a 4 input NAND using 2 off 2-input NANDS in
Figure 11.

Vcc (+5V)

Vin – ‘A’ P-Type CMOS

TR1 & TR2

Vout = A*B
Vin – ‘B’

N-Type CMOS
TR3 & TR4

A B Vout
0 0 1
0 1 1
1 0 1
1 1 0

Figure 8 Two-Input NAND gate. To add more inputs another P-type device is added in
parallel with TR1 & TR2 and another N-type device added in series with TR3 & TR4 –
the gates of the new devices connected together to form the new input.

One other disadvantage of this circuit is that the output impedance varies depending on the
number of parallel P-type CMOS FETS are on or off. To eliminate this effect an inverter is
added to the NAND output and will now form a AND gate. To restore the NAND function two
inverters in series need to be added to the output of the NAND gates as shown in Figure 10.
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Port
Vcc
Num=3
MOSFET_PMOS
MOSFET_PMOS
MOSFET4
MOSFET2
Model=MOSFETM2 LEVEL1_Model LEVEL1_Model
Model=MOSFETM2 Length=L um MOSFETM1 MOSFETM2
Length=L um Width=W um Vto=0.7 Uo=660 Vto=0.7 Uo=210
Width=W um
Kp=50e-6 Kp=50e-6
Gamma=0.6 Gamma=0.6
Phi=0.8 Phi=0.8
Lambda=LAMBDA Lambda=LAMBDA
Port Pb=0.95 Pb=0.95
A Cgso=220e-12 Cgso=220e-12
Num=1 Cgdo=220e-12 Cgdo=220e-12
Cgbo=700e-12 Cgbo=700e-12
Port Cj=770e-6 Cj=560e-6
OUT Mj=0.5 Mj=0.5
Num=2 Cjsw=5e-10 Cjsw=5e-10
Mjsw=0.38 Mjsw=0.35
Port Tox=140e-10 Tox=150e-10
B MOSFET_NMOS
Ld=0.016 um Ld=0.015 um
Num=4 MOSFET1
Model=MOSFETM1
Length=L um
Width=W um
Var
Eqn
VAR
VAR1
LAMBDA=0.1/L
MOSFET_NMOS L=1
MOSFET3 W=1
Model=MOSFETM1
Length=L um
Width=W um

Figure 9 ADS Transient simulation setup for a 2 input NAND gate. NOTE this version is
unbuffered and normally would have two inverters in series on the output.
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Vcc (+5V) Vcc (+5V) Vcc (+5V)

Vin – ‘A’ P-Type CMOS

TR1 & TR2

Vout = A*B

Vin – ‘B’

N-Type CMOS
TR3 & TR4 A*B
A*B

Figure 10 Buffered output 2-input NAND gate using CMOS inverters on the output. One inverter will realise a 2-input AND gate and another inverter
is added to restore the NAND function.
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4-Input NAND gate using 2-Input logic gates

A E
NAND G
B
NOR NOT

C H
NAND
D F

Figure 11 Realisation of a 4-input NAND gate using 2-input logic circuits

NAND 1 NAND 2 NAND NAND NOR NOT

A*B C*D E+F G
A B C D E F G H

0 0 0 0 1 1 0 1
0 0 0 1 1 1 0 1
0 0 1 0 1 1 0 1
0 0 1 1 1 0 0 1
0 1 0 0 1 1 0 1
0 1 0 1 1 1 0 1
0 1 1 0 1 1 0 1
0 1 1 1 1 0 0 1
1 0 0 0 1 1 0 1
1 0 0 1 1 1 0 1
1 0 1 0 1 1 0 1
1 0 1 1 1 0 0 1
1 1 0 0 0 1 0 1
1 1 0 1 0 1 0 1
1 1 1 0 0 1 0 1
1 1 1 1 0 0 1 0

Table 1 Truth table for the 4-input NAND gate using 2 input logic circuits
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XOR Exclusive OR gate

The exclusive OR gate differs from a normal OR gate in that the output is 1 if ‘ONE’ of the
inputs are one but not both of them. The truth table for the exclusive OR gate is shown below
and the gate circuit diagram is shown in Figure 12:-

A B C
0 0 0
0 1 1
1 0 1
1 1 0

This type of gate can be used as a digital phase detector in PLL (phase locked loop) systems.

A C
OR

AND

E
NAND
B
D

A B C D E
0 0 0 1 0
0 1 1 1 1
1 0 1 1 1
1 1 1 0 0

Figure 12 Showing XOR circuit and it’s corresponding truth table.

In a PLL circuit the phase detector XOR gate is fed by two digital signals. One signal comes
from the reference and the other from the VCO (voltage controlled oscillator). The operation
of the XOR gate is analogous to that of an analogue multiplier and will produce a triangle
wave output representing the phase error of the two input signals.