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Clocking
Clocking
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Outline
Introduction H-tree Zero skew clock DME and its extension New trends
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Introduction
For synchronized designs, data transfer between functional elements are synchronized by clock signals Clock signal are generated externally (e.g., by PLL) Clock period equation
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Clock Skew
Clock skew is the maximum difference in the arrival time of a clock signal at two different components. Clock skew forces designers to use a large time period between clock pulses. This makes the system slower. So, in addition to other objectives, clock skew should be minimized during clock routing.
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Power
very important, as clock is a major power consumer It switches at every clock cycle
Noise
Clock is often a very strong aggressor May need shielding
Delay
Not really important But slew rate is important (sharp transition)
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Buffer insertion
Clock buffers to reduce clock skew, delay, and distortion in waveform.
Wire sizing
To further tune the clock tree/mesh
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Clock trees
A path from the clock source to clock sinks Clock Source
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Clock trees
A path from the clock source to clock sinks Clock Source
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H-tree Algorithm
Minimize skew by making interconnections to subunits equal in length
Regular pattern
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DME needs an abstract routing topology as the input It has a bottom-up phase followed by a top-down process
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Bottom Up Phase
Each node v has a merging segment ms(v). A merging segment is a Manhattan arc Manhattan arc: has slope +/- 1 or has zero length (could be a point). tiled rectangular region (TRR): The collection of points within a fixed distance from a Manhattan arc. The intersection of two TRRs is a TRR Merging segments are always Manhattan arcs
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DME Wrapup
[Boese and Kahng, ASIC92]
DME is guaranteed to find the minimum wire length with zero skew under the linear delay model Need to have an abstract routing graph to start with
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Topology Generation
One common approach
Balanced and geometry guided Top down-partitioning that recursively divide the set of sinks, using alternating horizontal and vertical cuts The balance bipartition heuristic generates a topology that recursively divides the set of sinks into two subsets with equal total loading capacitance
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Trend
Clock skew scheduling together with clock tree synthesis
Schedule the timing slack of a circuit to the individual registers for optimal performance and as a second criteria to increase the robustness of the implementation w.r.t. process variation.
(P. Restle)
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