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CHAPTER I

INTRODUCTION

1.1 INTRODUCTION TO VLSI

A Very Large-Scale Integration (VLSI) has been pushed towards the

development of an integrated circuit by connecting a huge number of transistors
to a single chip. Developing the 3D IC could provide the possibility of reducing
interconnect delays and improving the execution framework. In addition, the
reduced wire length of the clock net reduces the utilization of the power circuit as
well as clock skew. It is a versatile method for implementing a heterogeneous chip
strategy system by synchronizing various methods, such as memory rationale
circuitry, optoelectronic gadgets, blended flag bits, radio frequency and so on.
The VLSI circuit technology might make significant progress from a small-scale
integration framework. This allows designers to build VLSI integration chips with
a billion transistor counts consecutively at tens of gigahertz. Rapid advancement
of integrated circuit technologies could not be accomplished without the use of
the computer-aided design process on board. Manufacturing a very large-scale
system produces a significant improvement in the integration process as soon as
possible. An exponential increase in the complexity of the circuits has added a
drawback to every VLSI design process that allows designers to adopt optimized
methods to solve problems in a very effective way. It covers the architecture,
functionality, logic, circuit, physical, manufacturing and packaging design
parameters of the integrated circuit system.
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Figure 1.1 Physical design flow of VLSI

Figure 1.1 shows the physical design flow of the VLSI design.
The input to the physical design phase includes a logical description below the
design phase of the system. The output of the process reaches the optimum or near
optimum configuration of the physical package in order to understand the
functional representation of the VLSI system. Usually, the issue of physical design
is combinatorial in nature, and the size of the problem was very large. Due to its
complexity, the physical design problem was split into sub-problems that could
be resolved/ addressed consecutively.
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The primary steps in the physical design stream of ASIC are:

 Design Netlist (after synthesis)
 Partitioning
 Floorplanning
 Placement
 Clock Tree Synthesis (CTS)
 Routing
 Physical Verification

Physical design usually directly influences the efficiency of the circuit,

area reliability, power and manufacturing capacity.

1.2 THREE DIMENSIONAL INTEGRATED CIRCUITS

Three-Dimensional Integrated Circuits (3D ICs) have rapidly

proven promising low-cost potential, high bandwidth, small area, low power and
enabled heterogeneous stacking (Knickerbocker et al. 2008; Lim 2010;
Van der plas et al. 2011 and Vardaman 2007). In 3D ICs, the Clock Distribution
Network (CDN) distributes the clock signal to all the sequential elements
throughout the stack. According to the International Technology Roadmap for
Semiconductors (ITRS) prediction, the clock skew must be less than 3% or 4% of
the clock cycle in an active clock network design (Source: www.itrs.net).
Therefore, in 3D clock network design, clock skew control, which was well
established in 2D ICs (Restle et al. 2001), is still a primary objective.
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Figure 1.2 Three dimensional integrated circuits

Figure 1.2 shows Three Dimensional Integrated Circuits. Using

through-silicon vias (TSVs), the clock signal in 3D ICs will not only transmit in
the X and Y directions, but also in the Z direction. The CDN travels the
whole chip, drives large capacitive loads and switches at a high frequency,
(Friedman 2001 and Restle et al. 2001) resulting in an increasing proportion of
the total power dissipated in the CDN. The clock network itself is responsible for
25 percent (Friedman 2001) and even up to 50 percent (Zhu 2003) of total power
consumption of chip in some applications. In addition, because a large clock slew
may cause a setup or hold time violation, the clock slew must also be taken into
account when designing a 3D clock network. Therefore, low power, skew and
slew remain important design objectives in 3D clock networks.

1.3 THROUGH SILICON VIA (TSV)

TSVs are vertical vias through the silicon die and provide die-to-die
connectivity for several functional networks, such as clock networks, power and
ground networks and signal networks. TSVs are a major task for interconnecting
devices on different layers, but they could cause some issues. TSVs generate
serious blockages for 3D clock routing in TSV-based 3D ICs. If a large number
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of TSVs were employed, this would lead to higher area consumption and an
increase in the final cost of the chip. The vertical integration process in 3D IC
provides an encouraging solution to reduce power and delay even though the
improved transistor density has become independent in expensive processes.
Vertical integration between layers could be recognized by the use of TSV. It is
an effective metal substrate that infiltrates the silicon substrate into engrossed
metal pads in the 3D system. Additional third-dimensional connectivity would
significantly reduce wire delay power and provide high data transfer density.

1.4 CLOCK TREE SYNTHESIS

Clock Tree Synthesis is a process that ensures that the clock is evenly
distributed to all sequential design elements. The objective of CTS is to minimize
skew and latency. Placement data will be provided as input for CTS, along with
the clock tree constraints. Constraints of the clock tree are Latency, Skew,
Maximum transition, Maximum capacitance, Maximum fan-out, list of buffers
and inverters, etc. The synthesis of the clock tree includes the construction of the
clock tree and the balance of the clock tree. Clock tree can be built by clock tree
inverters in order to maintain the exact transition (duty cycle) and clock tree
balancing is done by clock tree buffers (CTB) to meet the skew and latency
requirements. To meet the area and power constraints, fewer clock tree inverters
and buffers should be used.

1.5 CLOCK SKEW

Clock skew is defined as the maximum difference in the time of arrival

of the clock signal from the clock source to all the sinks. In circuit design, Clock
skew can be caused by a variety of factors, such as wire-interconnect length,
variation in intermediate devices, temperature variations, material imperfections,
capacitive coupling and differences in input capacitance on clock inputs of devices
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using the clock. As a circuit's clock rate increases, timing becomes more critical
and less variation can be tolerated if the circuit is to operate properly.

There are two types of clock skews: negative skews and positive skews.
Positive skew occurs when the transmitting register receives a clock tick earlier
than the receiving register. Negative skew is the opposite: the receiving register
will have the clock ticked earlier than the sending register. Zero clock skew refers
to the occurrence of the clock tick at the moment of transmission and reception of
the data.

1.6 CLOCK SLEW

Large parasitic capacities of TSVs in 3D ICs result in increased signal

slew and delay. For high-speed clocking, clock slew rate control is an important
reliability issue. If the slew rate is too low, i.e. if it takes too long for the clock
signal to rise or fall, set-up and hold times may be broken. This hold time violation
can not be fixed with a lower clock frequency.

1.7 CLOCK GATING LOGIC

Today's consumer needs more functionality, energy-efficient

equipment and optimized power devices as time passes, so to optimize the power
of the device, the easiest control technique is to turn off the clock of the sequential
block of the device when there is no operation needed from that section for a
certain duration.

Clock Gating is a technique that can be used to control the dissipated

power of Clock Net. The clock net is responsible for large part of the power
dissipation in synchronous digital circuits (up to 40 percent) (Dobberpuhl et al. 1992).
Clock gating limits the unnecessary switching on the clock net parts by disabling
the clock.
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Gated Clock is an easily accepted technique for optimizing power and

can be applied at system and gate level. Clock Gating can save more power by not
clocking the register if its state is not changed. Clock consumes power
continuously because it toggles the registers and their associated logic. The clock
gating shuts off the clock while the system maintains its current state in order to
reduce power consumption.

1.8 CLOCK DISTRIBUTION NETWORKS

Today, almost all major designs are synchronous circuits in which

operations and data transmission are controlled by a clock signal. For these circuits
to function as expected, a clock signal must be distributed to each latch and
flip-flop in a design that meets certain measurements of clock quality such as slew,
skew, and jitter (Mule et al. 2002). Slew is the rate at which the clock signal varies
during a transition. As long as the clock drivers are properly sized and do not drive
excessive loads, this measure is only a concern at high clock frequencies.

During the circuit operation, the skew between two points does not
change and can only be changed during the design phase. Jitter is a cycle-to-cycle
instability in the clock signal's arrival time caused by variations in power supply,
thermal noise, and capacitive crosstalk. During the design phase, Jitter can not be
determined or modified. As a result, jitters need to be added to the cycle time
budgets for critical paths. The main focus is the design of the CDN since it has the
greatest impact on skew. There are many choices to implement clock networks,
and all tradeoff between skew and power. In other words, the lowest skewed
networks often require the most metal to evenly distribute the clock signal, thus
consuming the most power. This is another power-versus-performance battle that
is seen in electronic design being played out every day.

The main objective of any CDN is to ensure that the clock signal
reaches the data registers (also referred to as flip-flops, clock sinks or leaf nodes)
exactly at the same time. If this is possible, the clock network will have zero skew.
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Of course, it is essentially impossible for there to be zero skew in the clock

network, so that effort is made to minimize skew while maintaining a reasonable
use of power. The main causes of skewing are variations in the length of the clock
routing connecting sinks as well as discrepancies in the loads driven by these lines.
Efforts to develop appropriate networks are aimed at minimizing the difference in
the length of the clock routing between the sink (as in trees) or at minimizing the
effect of the difference in load (as in mesh).

Clock distribution networks can have a major impact on system-wide

efficiency and reliability. In order to achieve a minimum skew, the CDN should
also try to obtain a slew rate as high as possible. Slew rate is the maximum rate of
signal change in a circuit. It depends on how long it takes for a signal to rise from
10% to 90% or drop from 90% to 10% of the supply voltage. Power consumption
and dissipation of power are also significant factors in the CDN.

Symmetric Clock Trees

By implementing a tree structure, the most common method of

clocking a large system is to distribute the clock across the chip with minimal
skew. There is a clock input in the general tree that serves as the root for the
design. The signals are going to fan across the chip from this root. After this signal
is routed to the subsection of the die, it will fan out again The number of fanouts
at each layer of the clock will be the same throughout the chip in a symmetric
clock tree and will occur at geometrically symmetric points on the die. Typically,
there is a buffer at each fanout point to drive the next lines. This enables tighter
control of the skew and protects against signal degradation (Friedman 2001).
A simple example of a buffered tree is shown in Figure 1.3.
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Figure 1.3 A three-level, fanout-of-three clock distribution network

In general, symmetric trees are often given names based on the shapes
the clock routes make. The H-Tree and the X-Tree are two such examples as
shown in. Figure 1.4 (a) and Figure 1.4 (b). The center point of the structure is fed
by a buffered clock signal in both of these tree types. This then fans out to the
center points of the four quadrants of the chip where another buffer is driving a
smaller structure. This will continue until a local buffer drives the clock sinks for
several levels of progressively smaller structures. Using this technique, each clock
signal has traveled the same distance with symmetrically sized buffers and
undergone the same insertion delay. Thus, for each leaf node, most trees try to
eliminate the difference between the routing lengths. However, due to load
mismatch at the sinks of the clock and process variations in the metal lines and
drivers, skew will still be present (Friedman 2001).

The metal widths of each successive clock layer must be tapered in

unbuffered tree clock distributions to minimize reflection of a high-speed clock
signal at the branching points (Friedman 2001).This is shown in Figure 1.4 (c).
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Figure 1.4 Clock distributions: (a) H-tree, (b) X-tree and (c) Tapered
H-tree

1.9 PROBLEM IDENTIFICATION

These days, 3D physical design is a predominant solution in high-

performance computing systems. In physical design, CTS plays a significant role
in the total performance of the chip, especially after placement. TSV based 3D
integrated circuits (3D ICs) provide a great challenge to the IC designers.
Designers have the ability to accomplish a significant number of benefits towards
utilizing TSVs, for example, shorter wire length, minimum wire delay, low skew,
less power and smaller chip area. TSV is a vertical electrical interconnection
passing through silicon. For short interconnected length and smaller package size
TSV is most important in 3D ICs. To design high-performance clock Tree, the
buffer size, selection of buffer, skew reduction, slew control and power
minimization are the most dominant factors because CDN determines the clock
skew. The difference in the delays between the output of the clock buffer and the
inputs of the clocked elements on integrated circuit is called clock skew. Clock
skew arises from the interconnected delays due to load mismatch. Clock skew is
a major dominant factor in determining the clock period.

Selecting the buffer size is an effective way to reduce the skew due to
interconnectdelays. In order to optimize the power, clock gating logic is an
important consideration in the performance of digital system. Clock gating
technique is not only responsible for reducing the power but also for reducing
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unwanted switching on the clock nets. Uncertainties in the clock timing lead to the
failure of the system.

1.10 OBJECTIVES

The objectives of the present research work are:

 To reduce the clock skew in 3D gated CTS using clock gating logic
with TSV-TSV coupling model.
 To improve the slew rate in 3D gated CTS using clock buffer, TSV
buffers, and clock gating logic.
 To analyze the performance for Low power CTS using Clock
Distribution Techniques.

1.11 THESIS ORGANIZATION

The rest of the thesis is organized as follows

Chapter 2: Literature Review
This Chapter presents a literature review to provide necessary
background for a general understanding of the challenges related to CTS and
CDN.

Chapter 3: Clock Gating Logic for Logic Circuits

This chapter presents Clock gating logic and its importance for CTS.
A detailed discussion on the simulation results is presented.

Chapter 4: Low Power Slew Aware 3D Gated Clock Tree Synthesis

This Chapter describes Low power and Slew aware gated CTS process
for 3D ICs using 3D-MMM Algorithm and also presents Slew aware buffering
with clock gating logic on TSV-TSV coupling model. A detailed discussion on
the simulation results is presented.
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Chapter 5: Slew and Skew Analysis Using Clock Distribution Techniques

This chapter presents Slew and Skew analysis by using three different clock
tree structures.

Chapter 6: Conclusion and Future Work

This chapter presents the Conclusion and also summarizes the
outcomes of the research work and outlines possible directions for future work.