Electrical Machines I

Prof. Krishna Vasudevan, Prof. G. Sridhara Rao, Prof. P. Sasidhara Rao

Phasor diagrams
I1

r1

jxl1

r2

jxl2

Io Ic
V1
Rc

Im
jXm

V2

ZL

(a)

I1 Ic V1 Rc

I2

r1

jxl1

r2

jxl2

I1

jX

I2

Io Im

R=r1+r2

ZL
jxm

V2 x=xl1+xl2

V1

V2

I1=I2
(c)

(b)

Figure 16: Exact,approximate and simplied equivalent circuits

The resulting equivalent circuit as shown in Fig. 16 is known as the exact equivalent circuit. This circuit can be used for the analysis of the behavior of the transformers. As the no-load current is less than 1% of the load current a simplied circuit known as approximate equivalent circuit (see Fig. 16(b)) is usually used, which may be further 41

Indian Institute of Technology Madras

Electrical Machines I

Prof. Krishna Vasudevan, Prof. G. Sridhara Rao, Prof. P. Sasidhara Rao

simplied to the one shown in Fig. 16(c).

On similar lines to the ideal transformer the phasor diagram of operation can be drawn for a practical transformer also. The positions of the current and induced emf phasor are not known uniquely if we start from the phasor V1 . Hence it is assumed that the phasor is known. The E1 and E2 phasor are then uniquely known. Now, the magnetizing and loss components of the currents can be easily represented. Once I0 is known, the drop that takes place in the primary resistance and series reactance can be obtained which when added to E1 gives uniquely the position of V1 which satises all other parameters. This is represented in Fig. 17(a) as phasor diagram on no-load.

Next we proceed to draw the phasor diagram corresponding to a loaded transformer. The position of the E2 vector is known from the ux phasor. Magnitude of I2 and the load power factor angle 2 are assumed to be known. But the angle 2 is dened with respect to the terminal voltage V2 and not E2 . By trial and error the position of I2 and V2 are determined. V2 should also satisfy the Kirchos equation for the secondary. Rest of the construction of the phasor diagram then becomes routine. The equivalent primary current I2 is added vectorially to I0 to yield I1 . I1 (r1 + jxl1 )is added to E1 to yield V1 . This is shown in g. 17(b) as phasor diagram for a loaded transformer.

42

Indian Institute of Technology Madras

Electrical Machines I

Prof. Krishna Vasudevan, Prof. G. Sridhara Rao, Prof. P. Sasidhara Rao

V1 IoX l1 E1 Ior1 E2

Io Im
V1 I1X l1

Il

(a)No-load

E1 I2

I1r1 E2 Il Io
(b)On-load

I2x2 I r 2 2

I2 V2

Figure 17: Phasor Diagram of a Practical Transformer

43

Indian Institute of Technology Madras