VHDL-rnekler

Shift Register
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Shift_register_VHDL is
port( Clock: in std_logic;
L,w: in std_logic;
Output: out std_logic_vector(3 downto 0);
Input: in std_logic_vector( 3 downto 0));
end Shift_register_VHDL;
architecture Behavioral of Shift_register_VHDL is
signal temp: std_logic_vector(3 downto 0);
begin
process
begin
wait until Clock'event and Clock='1';
if L='1' then
temp <= Input;
else
for i in 0 to 2 loop
temp(i) <= temp(i+1);
end loop;
temp(3) <= w;
end if;
end process;
Output <= temp;
end Behavioral;

RAM
--------------------------------------------------------------- a simple 4*4 RAM module (ESD book Chapter 5)
-- by Weijun Zhang
--- KEYWORD: array, concurrent processes, generic, conv_integer
-------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------entity SRAM is
generic(
port(

width:
depth:
addr:

integer:=4;
integer:=4;
integer:=2);
Clock:
in std_logic;
Enable:
in std_logic;
Read:
in std_logic;
Write:
in std_logic;
Read_Addr: in std_logic_vector(addr-1 downto 0);
Write_Addr: in std_logic_vector(addr-1 downto 0);
Data_in:
in std_logic_vector(width-1 downto 0);
Data_out: out std_logic_vector(width-1 downto 0)

);
end SRAM;
-------------------------------------------------------------architecture behav of SRAM is
-- use array to define the bunch of internal temparary signals
type ram_type is array (0 to depth-1) of
std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;
begin
-- Read Functional Section

ROM
--------------------------------------------------------------- 32*8 ROM module (ESD Book Chapter 5)
-- by Weijun Zhang, 04/2001
--- ROM model has predefined content for read only purpose
-------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ROM is
port( Clock : in std_logic;
Reset
: in std_logic;
Enable
: in std_logic;
Read
: in std_logic;
Address
: in std_logic_vector(4 downto 0);
Data_out: out std_logic_vector(7 downto 0)
);
end ROM;
-------------------------------------------------------------architecture Behav of ROM is
type ROM_Array is array (0 to 31)
of std_logic_vector(7 downto 0);
constant Content: ROM_Array := (
0 => "00000001",
1 => "00000010",
2 => "00000011",
3 => "00000100",
4 => "00000101",
5 => "00000110",
6 => "00000111",
7 => "00001000",
8 => "00001001",
9 => "00001010",
10 => "00001011",
11 => "00001100",

-- Suppose ROM has

-- prestored value
-- like this table
----------

Kaynaklar

http://en.wikibooks.org/wiki/VHDL_for_FPGA_
http://esd.cs.ucr.edu/labs/tutorial/