EECS 413 Final project, Fall 2003. Instructor: M.

Flynn

A 2.5 V high gain CMOS differential input, differential output single stage amplifier.
B. Li, Z. Hua, H. Pham
different function blocks of the design. Section III emphasizes the underlying circuit analysis. Section IV displays the final circuit implementation, and finally, section V shows the simulated results using Cadence. II. CIRCUIT DESCRIPTION A. Architecture overview The topology of fig.1 is chosen.

Abstract A high gain, high frequency single stage CMOS op amp is designed and simulated. The authors used gain boosting technique and common mode feedback circuitry on a differential input/ouput 0.5m CMOS amplifier. Results comprehend a DC gain of 110 dB, a unity-gain frequency superior to 300MHz associated with a phase margin in the range of 60 degrees. Good insensivity to temperature, voltage rail level (2.5V +/- 10%) and common monde input voltage variations has been demonstrated. Index Terms CMOS opamp, speed, high DC gain, gain boosting.
I.

INTRODUCTION

Among the desired features of analog circuits, speed and accurary are in high demand. In order to obtain those, high unity gain frequency and a single pole settling behavior on the one hand, and high DC gain on the other hand have to be achieved respectively. The combination of high unity gain frequency and high DC gain entails tradeoffs in the design. High unity gain frequency requires a single stage design, whereas high DC gain requires multistage topologies. Previous works for gain enhancement include cascoding for high DC gain obtainment without affecting the unit gain frequency [1], dynamic biasing of transconductance amplifiers [2] where the bias current is adjusted to get high DC gain - but still no so good high unit gain frequency, triple cascoding which yields high gain but extra poles and limited output swing [3]. Positive feedback has also been used to increase the DC gain with matching problems [1]. This work on a CMOS differential input, differential output amplifier is based upon the gain boosting principle used in [4]. We aim at a high DC gain of at least 90dB, a minimum high unit gain frequency of 300MHz. Stability, and fast settling behavior are desired as a phase margin of 60 degrees is targeted. Care is given concerning the output swing voltage, which should be equal to 0.8V (1.25+/-0.4). Finally, a single current source and single 2.5V voltage source are provided. Section II describes the circuit topology and the roles of the
This work was carried out in the framework of the Fall 2003 EECS413 final project at the University of Michigan. The authors can be reached at binl@umich.edu, zhua@umich.edu and hpham@umich.edu.

Fig 1. Overall topology A modified main stage amplifier based on [4] constitutes the core of the circuit, its task is to push the unity gain frequency as far as possible, while maintaining a good stability. The accompanying blocks: 2 top feedback amplifiers and 2 bottom ones will boost the DC gain as will be explained in subsection C. B. Main stage amplifier and CMFB The main stage amplifier proposed in [4] is adopted. It consists of a folded-cascode amplifier with PMOS input transistors for high voltage output. This structure has been elected because it provides high gain, and can be reproduced easily in the feedback blocks for gain enhancement. The other critical role of the main stage is to determine the unit gain frequency. One weakness of the design proposed in [4] is that the output CM level is sensitive to device properties and mismatches. For instance, minute current unbalances can force the transistors used as current source into triode region. As differential feedback cant stabilize high gain differential pairs, we propose to add a common mode feedback (CMFB) circuit at the differential output nodes of the initial main stage to increase the linearity of the main stage. The CMFB will sense the ouput CM 1

EECS 413 Final project, Fall 2003. Instructor: M. Flynn level, compare it with a set reference and return the error to the amplifiers bias network. We note that the CMFB will introduce another pole at high frequency that can degrade the stability. The chosen configuration for the CMFB appears in fig.2 [5] [6].

2 four individual feedback stages consumes a lot more extra space. Thus, we modified the feedback amplifiers as differential inputs to single end output structure combined with active current mirror to circumvent the need of CMFB. To achieve both high impedance and low headroom consumption, the low-voltage cascode design is applied for the current mirror component. The schematic of the top and bottom feedback stages are illustrated in fig.4.

Fig2. Folded cascode of main amp with CMFB Vb is defined by a current mirror. If we set (W/L)M13=(W/L)M8, and (W/L)M10=2(W/L)M1=2(W/L)M12, then Id8=I1 only if Voutcm= Vref. Hence the ouput level becomes independent of device parameters and values of Vb. Furthermore, Vd13=Vd18 is forced via the copy of M6, M7 in the set of M15, M14. The sizes of M10, M12, and M11, are chosen such that (W/L)M10=2(W/L)M11=2(W/L)M12 and large enough so that these transistors remain in the triode region. C. Gain boosting feedback The addition of the feedback amplifiers is illustrated in fig.3. Fig.4. Top feedback (left)/ bottom feedback (right)schematic III. CIRCUIT ANALYSIS The requirements of the project are 90 dB DC gain, 300MHz unity gain frequency and 0.8V voltage swing. Those specifications guide us to determine the size of transistors and bias voltage. In this project the whole single stage amplifier is divided into 2 parts: one main stage amplifier and feedback amplifiers to boost gain. So the analysis is divided into two parts. The main amplifier has to have at least 45dB gain and its unity gain frequency has to be larger than 300MHz because u of whole amplifier is determined by the main one. The feedback ones are also required to have at least 45dB gain. But it can be a little slower as long as its unity gain frequency is larger than the frequency of first pole of main one. The following are the steps we go through to determine the parameters. A. Main stage amplifier Fig.3. Feedback stage for gain-boosting The feed back stage drives the gate of T2 and forces the drain voltage of T1 to approach Vref, which significantly reduces the effects of voltage variation at output (V0) on the drain voltage of T1 and thus the current through T1. As a result, the output impedance is increased by the gain of the feedback stage, so is the overall gain of the single stage amplifier. Av = Gm Rout g m1 ( Aadd g m 2 ro 2 ro1 ) (1) This cascode structure with this gain boosting technique is also called regulated cascode because the feedback stage regulates the drain voltage of T1. Similar to the main stage differential pair, the feedback amplifier we proposed is also a folded cascode. As mentioned previously, common mode feedback is often required for high gain cascode differential pair, but incorporating CMFB into Fig.5. Schematic of Folded cascode with CMFB 1) Unity gain frequency There are two important poles for this stage when the feedback amplifiers are added. One is the pole at the output load and another is the pole at the source of M5. Unity gain

EECS 413 Final project, Fall 2003. Instructor: M. Flynn frequency is determined by the first pole and can be calculated by the following formulas: (2) u = gm/CL=2fu where fu is the unity gain frequency, CL is the load capacitance and gm is the transconductance of input transistors (M7 and M8) The unit gain frequency is required to be over 300MHz, hence: (3) gm =2*fu* CL Once gm is determined as being equal to 3.8mS for a 2pF load, W/L ration of input transistor can be determined by the following equation:

3 together later on, it is necessary to determine the bias voltages of those transistors. For the bias voltage of M9, Vg, M9-Vth,M9 - Vds, M11 >Vds, M9. When body effect of M9 is considered and Vth,M9=.7V, Vg, M9,min=.2+.3+.7=1.2 At the same time, we want M9 saturated and output~1.25V. Vg, M9,max=1.25+.7-1=1.85 Vout1> Vg, M9-Vth,M9+100mV The bias voltage chosen is (Vg, M9,min +Vg, M9,max)/2=1.5V For the bias voltage of M5 Vdd- Vds, M3-Vg, M5-Vth,M5 >Vdsat, M5. When body effect of PMOS M5 is not needed to consider and Vth,M5=.5V, Vg, M5,max=2.5 -.6-.5-.4=1.0V At same time, we want M9 is saturated Vg, M5,max=1.25-.5-1=0.85 Vout1< Vg, M5+Vth,M5-100mV The bias voltage chosen is (Vg, M5,min +Vg, M5,max)/2=.9V As for M11, M12, the bias voltage is not so critical. We just want to use a current mirror to copy 100A current to here. So, a current mirror is implemented. It is just routine calculation. The details are not shown here.

gm =

2I d Vgs Vth

(4)

Initially, Vdsat can be set at 200mV and after calculation Id=380A for M1 and M2. The size of M1 and M2 are calculated with: Id=

Cox n is chosen to be equal to 190mA/V2, and W/Lequal to

40. For the voltage current transistor below the input ones, its size can also be calculated W/L=80. Basically the gain of this folded cascode with common mode feed back (CMFB) is mainly determined by the folded cascade, and is around ( g m ro ) . As we know g m ro ~
2

1 W Cox n (Vgs Vth ) 2 2 L

(5)

WL / I d , to

increase gain the current should be small. With this consideration in mind, the current through M5, M9 and M11 are set at 380A/4~100 A. Id of M3 is about 480 A. Since M3 and M5 are PMOS transistors, their Vdsat are set a litter higher. Vdsat, M3=500mV, Vdsat, M5=300mV. Vdsat of M9 and M11 are set at 200mV because they are NMOS transistors. After calculation, the initial values of W/L are put in table 1. Trans M1 Cur M3 M5 M9 M11 W/L 40 80 80 42 26 26 Table1. Summary of main stage transistor size ratio. 2) Voltage swing. In this project, the voltage swing is at least .8V. The swing is limited by the requirement of maintaining the transistors saturated. In order to make M9 and M11 saturated, Vout1>Vds, M11+Vds,M9 and in order to make M5 and M3 saturated, Vout1<Vdd-Vds,M3-Vds,M5. From this the voltage swing can be determined as following, (6) Voltage swing= Vdd-Vds,M3-Vds,M5-Vds, M11-Vds,M9 Since Vdsat of those transistors are set from last section, and since Vds=Vdsat+100mV, Voltage swing~2.5-.6-.4-.2-.2=1.1V With this design we should be able to satisfy the requirement of voltage swing. 3) Voltage biasing In the single amplifier design, the bias voltages of M9, M10, M5 and M6 are provided by feedback amplifier. Since we built main stage and feedback amplifier separately and built them

Fig.6. Bias Circuit for main stage amplifier The biasing of M3, M4 are critical for the performance of the overall circuit. The bias circuit is adopted from Razavi [6]. Vgs of M17 is used to set the bias voltage for M3 and M4. Id,M17=Id,M14=2*Id,M1=2*380/480*Id,M3. (W/L)M17=1.6*(W/L)M3. As explained before, sizes of M15, M16 are same as M1 and M2. Size of M14 is same as the size of current source below M1,2. (W/L)M13=2(W/L)M7. Trans W/L M13 M14 M15 M16 30 80 40 42 Table2. Size for the bias circuit M17 108

4) High gain and phase margin: role of poles. The gain of main stage is about ( g m r0 ) . Usually g m r0 is in order of 20. So the gain of folded cascode can reach 52 dB which satisfies the requirement of 50 dB. Phase margin is required to be above 60 degrees for stability reason. In the design, it requires frequency of the second pole 2 is superior to be 3 u. 2 is due to the cascode node at the main stage amplifier. In our simulation we can decrease the size of M1 and
2

EECS 413 Final project, Fall 2003. Instructor: M. Flynn M2 to increase 2. B. Feedback The gain of the feedback stage in fig. 4 is designed to be half of the overall gain (e.g. 45dB). It is given by the following equation.

4 and M9, 10 in Fig 5. were checked in the simulation. They are 1.0V and 1.43V respectively, both in the range of calculation.

Av g m1 {[g m3 ro 3 (ro1 || ro 5 )] || [g m 7 ro 7 ro 9 ]} (7)

Unlike the main stage fully differential pair, the feedback stage has its output connected with the transistor gate and thus does not exhibit the dominant pole as the main stage due to capacitance loads. In another word, gm1 is not necessarily high to ensure a high overall unity gain frequency. This implies that the currents and the transistor sizes can be reduced in the feedback stage compared with the main stage. The power and space consumption is therefore significantly reduced, while the gain is still maintained because of increased ro. Based on the above analysis we set the currents and initial transistor sizes of the feedback amplifiers and tweak them to ensure that each transistor has a Vdsat above 200 mV and operates in saturation. Biasing is an important issue to enable the feedback amplifier operating properly. Vbias1 = Vdd/3 and Vbias2 = 2Vdd/3 are chosen to provide the bias for the common gate stage and active current mirror in the feedback amplifier. As mentioned previously, the feedback amplifier regulates its Vin from the main stage to approach Vref, which needs to be carefully chosen for the proper operation of the main stage. The voltage at the cascode folding node of the main stage operating in static state with zero small signal input becomes natural choice. Instead of employing external voltage supply as bias, we take the benefit of differential pair structure by using the voltages of cascode folding nodes at each side of the main stage as the input of its feedback stage at the same side and the reference (Vref) of its feedback stage at another side. This cross reference method is expected to double the gain of otherwise a constant Vref since the voltages at the two folding nodes of the main stage provide a differential input to the feedback stage. The top and bottom feedback amplifiers have the same structure, but are different in implementation because they are connected to different parts of the main stage. The top one has a high common mode voltage input and low output while the bottom one has a low common mode voltage input and high output. We inverted the top feedback amplifier between Vdd and Vss to construct the bottom feedback amplifier. The P/N type of each individual transistor also needs to be switched. IV.
RESULTS

Fig.7. Final main stage amplifier.

Fig.8. Top feedback amplifier schematic

Fig.9. Bottom feedback amplifier schematic B. Simulation results 1) Main stage amplifier: The main stage amplifier has been simulated separately from the feedback. The gain of main state is 57 dB and its unity gain frequency is 310MHz. Its phase margin is about 68 degrees. This fulfills our requirement.

A fully differential CMOS has been implemented using a 0.5 m CMOS process for accuracy purposes, a single 1.2mA current source, and 2.5V power supply. A. Circuits implemented with sizes Initial transistor sizes were modified moderately to achieve targeted specifications. The bias voltages for transistors M5, 6

EECS 413 Final project, Fall 2003. Instructor: M. Flynn

5 4) Final single stage amplifier When we put main stage block and feedback amplifier together, the simulation are made at different temperatures, Vdd and Vcm. Sample plots are provided in fig.12 and fig.13. The total power consumption is moderate, about 22mW.

Fig.10. Main stage amplifier performance 2) Top and bottom feedback stage. As shown in fig.11, the top and bottom feedback stages demonstrate low frequency gain of 58 dB and 52 dB, respectively. The values are close to that of the main stage, and half of the overall gain in dB. As desired, the dominant pole appears at about 10MHz, significantly larger than that of the main stage, and stability problem doesnt arise.

Fig.12. AC behavior at 27C, for Vdd=2.25,2.5,2.75V

Fig.11. Top and bottom feedback performance 3) Comparisons with expected theoretical gains. Using equation (7), theoretical gains can be predicted as individual transistor properties can be provided by Cadence. Table 3 compares the simulated and theoretical gains for the individual blocks of the design. They fit excellently. Expected Simulated Error gain gain percentage Main stage 57.4dB 58dB 1% Top feedback 57dB 58dB 1.7% Bottom feedback 50.4dB 51.5dB 2.1% Table3. Comparison between theoretical and simulated gains As the gain boosting feedback mainly operates from the top of the main stage, we can predict an overall gain of 114.4dB, which is very close to the simulated results. Fig.13. AC behavior at 85C, for Vdd=2.25,2.5,2.75V Results are summarized in table 4. Temp 27C 27C 27C 27C 27C 85C 85C 85C Input Vdd Gain Phase common (V) (dB) margin mode (V) (deg) 1.6 2.25 115.7 70 1.6 2.5 121.1 70 1.6 2.75 91.63 58 1.2 2.5 122.4 72 2 2.5 120.6 70 1.6 2.25 105.6 71 1.6 2.5 115.6 72 1.6 2.75 90.6 62 Table4. Performance summary Unity gain frequency (MHz) 387 434 369 403 436 312 353 338

EECS 413 Final project, Fall 2003. Instructor: M. Flynn C. Implemented layout The main amplifier and the feedback were laid out individually first, and then assembled. The total area for the layout is 130m *180m. The final layout (fig.13) passed the DRC and LVS test, with parasitics extracted. and Brian Duverneay for CAD insights. REFERENCES
[1]

[2] [3] [4] [5] [6]

C. A. Laber et al, A positive-feedback transconductance amplifier with applications to high-frequency, high-Q CMOS switched-capacitor filters, IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1370-1378, Dec. 1988. M. G. Degrauwe et al, Adaptive biasing CMOS amplifiers, IEEE J. Solid-State Circuits, vol. SC-17, pp. 522-528, June 1982. H. Ohara et al., A CMOS programmable self-calibrating 13-bit eight -channel data acquisition peripherial, IEEE J. Solid-State Circuits, vol. SC-22, pp. 930-938, Dec 1987. K. Bult et al, A fast-settling CMOS Op Amp for SC circuits with 90-dB DC gain, IEEE J. Solid-State circuits, vol. 25, no. 6, Dec. 1990. Razavi, pp. 323 on CMFB. Gray, Hurst, Lewis and Meyer, section 12.5 on CMFB.

Fig.13. Final layout for single stage amplifier. Table 5 shows the achieved improvement when the parasitics are extracted and the layout resimulated in nominal conditions of operation. Before parasitics extraction 121.1dB 434MHz After parasitics extraction 122.87dB 475MHz Changes

DC gain 1.5% Unity gain 9.4% frequency Phase 69.8 deg 70.5deg 1% margin Table5. Impact of parasitics extraction on main performances V. CONCLUSION Using gain boosting technique and common mode feedback, the authors managed to improve the original design given by [4]. The design is robust, and demonstrates good stability with temperature, Vdd, input common voltage variations. All projected specifications have been satisfied. APPENDIX ABOUT LINKS Final stage schematic for simulation: group12/main_amp/finalsetup Layout: Layout: group12/main_amp/ huasetup Schematic: group12/main_amp/huasetup ACKNOWLEDGMENT The authors thank Prof. Flynn for feedback on the design, 6