The Flipped Voltage Follower (FVF)

A useful cell for low-voltage, low-power circuit design

A.Torralba1
J. Ramrez-Angulo2, R.G.Carvajal 1, A. Lpez-Martn 3,
1Dpto.

de Ingeniera Electrnica, Escuela Superior de Ingenieros, Universidad de Sevilla, (SPAIN) 2Klipsch School of Electrical Engineering, New Mexico State University, (USA) 3Dpto. de Ingeniera Elctrica y Electrnica, Universidad Pblica de Navarra, Pamplona (SPAIN)

Antonio Torralba, Texas A&M, College Station, June 2004

Contents
1. Introduction. 2. The Basic FVF. 3. FVF Structures. 4. Applications. 5. Conclusions.
Antonio Torralba, Texas A&M, College Station, June 2004

1. Introduction
Portable and mobile, battery-operated devices. Power consumption in digital blocks is highly dependent on the supply voltage (P VDD2). This forces to decrease the supply voltage in mixed-signals ASICs.

Downscaling of technology forces VDD to decrease but VT does not scale in the same way.

In the near future

VDD < VTn + |VTp|

Antonio Torralba, Texas A&M, College Station, June 2004

1. Introduction
Even very simple circuits do not work under this condition

VDD < VTn + |VTp|

New design techniques and new circuit structures are required for low voltage, low power design
Antonio Torralba, Texas A&M, College Station, June 2004

2. The Basic FVF

a) Conventional Voltage Follower b) Flipped-Voltage Follower (FVF)

Sourcing a) Conventional b) FVF Ib HIGH

Sinking HIGH Ib

Av <1 =1

gout gm1 gm1 gm2 ro1

[Ramirez-Angulo92] J.Ramrez-Angulo, R.G.Carvajal, A.Torralba, J.Galn, A.P.VegaLeal, and J.Tombs. The Flipped Voltage Follower: a useful cell for low-voltage low power circuit design, Proc. ISCAS02, vol. 3, pp. 615-618, 2002. Antonio Torralba, Texas A&M, College Station, June 2004 5

2. The Basic FVF

Open Loop Analysis
Dc gain
AOL = Vr / VT = - gm2 ROLY ROLY = rb || gm1 ro1 ro2 , ROLX (1+rb/ro 1)/gm1 || ro2

Dominant Pole
At Y: wpY = 1 / CY ROLY

Non-Dominant Pole
At X: wpX = 1 / CX ROLX

Gain-Bandwidth Product
CX parasitics at node X (incl. LOAD) CY parasitics at node Y (incl. Cc if any) GB = gm2 / CY

Antonio Torralba, Texas A&M, College Station, June 2004

2. The Basic FVF

Stability Analysis
0

Stability Criterion: wpX > 2 GB

For Ib a simple current mirror (rb ro1)

97
0

CX gm1 < CY 4gm2

For Ib a cascode current mirror (rb gm1 ro1 ro2)

<

9U

&F
U E ,E

CX 1 < CY gm2 ro2

usually requires compensation

CX parasitics at node X (incl. LOAD) CY parasitics at node Y (incl. Cc if any)

Antonio Torralba, Texas A&M, College Station, June 2004

2. The Basic FVF

Closed Loop Output Resistance

0
;

RCLX =

YL 0
<

YR

ROX 1 + AOL

1 r 1 + b || ro2 gm1 ro1 gm2 (rb || gm1ro1ro2 )

For Ib a simple current mirror (rb ro1)

RCLX

2 gm1 gm2ro1

,E

For Ib a cascode current mirror (rb gm1 ro1 ro2) 1 RCLX gm1 gm2ro1

ACL 1 and RCLX is only a few Ohms (20 100) in all cases
Antonio Torralba, Texas A&M, College Station, June 2004

2. The Basic FVF

DC considerations
VDDMIN = VGSMIN + VDSsat 0.8 V for 0.6m CMOS technology. It is a lowvoltage cell. But, for large VDD, biasing M 2 in saturation is difficult for low vi. A high-voltage version includes a voltage shifter in the feedback loop [Chung-Chih95]

[Chung-Chih95] H.Chung-Chih, H.Changku, M. Ismail, CMOS low-voltage rail-to-rail V-I converter, Proc. 38th MWSCAS, vol.2, pp. 1337-1340, 1995.
Antonio Torralba, Texas A&M, College Station, June 2004

2. The Basic FVF

3-terminal cell (strong inv.)
Y<
Const

0
;

Relation

v X = vZ + f ( I b , iY ) vY = g ( I b , i X , iY , vZ ) iZ = 0 ; f (I b , iY ) = VTp + 2 (I b iY ) k p (W L)M 1

L ;

L =

Y=

0 Y; < L=0 \ Y<

For M 2 in saturation
g ( Ib , i X , iY , v Z ) = VDD VTp

2 (I b iY i X ) k p (W L )M 2

,E
M1 in saturation

For M 2 in ohmic
g (I b , i X , iY , v Z ) =VDD VTp v X I b iY i X 1 2 k p (W L )M 2 v X

The most interesting case is for iY = 0

Antonio Torralba, Texas A&M, College Station, June 2004

10

3.FVF Structures
, RXW X$

Current sensor (FVF-CS)

M2 saturation

M2 ohmic

M5 saturation

Antonio Torralba, Texas A&M, College Station, June 2004

11

3.FVF Structures
Non-Symmetrical Class-AB Differential Pair (FVF-NDP)

Antonio Torralba, Texas A&M, College Station, June 2004

12

3.FVF Structures
Symmetrical Class-AB Pseudo Differential Pair (FVF-PDP)
vinCM=(v3+v4)=V1

Antonio Torralba, Texas A&M, College Station, June 2004

13

3.FVF Structures
Symmetrical Class-AB Differential Pair (FVF-SDP)

Antonio Torralba, Texas A&M, College Station, June 2004

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3.FVF Structures. Summary

Current sensor (FVF-CS) Non-Symmetrical Class-AB Differential Pair (FVF-NDP)

Symmetrical Class-AB Pseudo Differential Pair (FVF-PDP)

Symmetrical Class-AB Differential Pair (FVF-SDP)

Antonio Torralba, Texas A&M, College Station, June 2004

15

3.FVF Structures. Summary

Current sensor (FVF-CS)
Non-Symmetrical Class-AB Differential Pair (FVF-NDP) Current sensor (FVF-CS)

Symmetrical Class-AB Pseudo Differential Pair (FVF-PDP)

Symmetrical Class-AB Differential Pair (FVF-SDP)

Antonio Torralba, Texas A&M, College Station, June 2004

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4.FVF-CS Applications
Current sensor (FVF-CS) Low voltage current mirrors

[Rijns93] J.J.F. Rijns, 54 MHz switchedcapacitor video channel equalizer Electr.Lett., vol. 29, no. 25, pp. 2181-2182, Dec. 1993

VinMIN = VDSsat Very low input resistance (a few Ohms)

[Ramirez-Angulo04] J. Ramrez-Angulo, R.G.Carvajal, A.Torralba, Low-supply voltage high-performance CMOS current mirror with low input and output voltage requirements, IEEE TCAS-II, vol.51, no. 3, pp. 124-129, March 2004.

Antonio Torralba, Texas A&M, College Station, June 2004

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4.FVF-CS Applications
Current sensor (FVF-CS) Low voltage current mirrors

Technology Minimum supply voltage Load resistor Bandwidth Input impedance Output impedance

0,35m CMOS AMS 1V 10 KOhm 120 MHz A few Ohms 1 GOhm 1.5 pA/vHz 20ns -66dB

[Torralba02] A. Torralba, R.G.Carvajal, J.Ramrez-Angulo, Output stage for low supply voltage CMOS current mirrors Electr.Lett., vol. 38, no. 24, pp. 1528-1529, Nov. 2002

Input referred noise (@10MHz) Settling time (1%, 4 A step) THD (10 A pp, @10KHz)

Antonio Torralba, Texas A&M, College Station, June 2004

18

4.FVF-CS Applications
Current sensor (FVF-CS) Other applications
IDD TEST CURRENT SENSOR LINEAR V-I CONVERTER

[Karthikeyan01] S. Karthikeyan, A. Tamminneedi, E.K.F.Lee, Design of low-voltage front-end interfaces for switched-opamp circuits, IEEE TCAS-II, vol.48, no. 7, pp. 722-726, July 2001. [Rout00] S. Rout, E.K.F.Lee, Design of 1 V switched-current cells in standard CMOS process, Proc. ISCAS, vol.2, pp. 421-424, 2000 SI Circuits Antonio Torralba, Texas A&M, College Station, June 2004

[Docudray03] G.O.Ducodray, R.G.Carvajal, J.Ramrez-Angulo, A high-speed dynamic current sensor scheme for IDD test using a FVF Proc. SSMSD, pp. 50-53, 2003

M2 I in M ( = HIGH) I b M B1 1

I M B2 b

I out

19

3.FVF Structures. Summary

Current sensor (FVF-CS) Non-Symmetrical Class-AB Non-Symmetrical Differential Pair Class-AB (FVF-NDP)

Differential Pair (FVF-NDP)

Symmetrical Class-AB Pseudo Differential Pair (FVF-PDP)

Symmetrical Class-AB Differential Pair (FVF-SDP)

Antonio Torralba, Texas A&M, College Station, June 2004

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4.FVF-NDP Applications
Non-Symmetrical Class-AB Differential Pair (FVF-NDP)
NON-LINEAR CLASS_AB TRANSCONDUCTOR
M 1P

CLASS-AB OUTPUT BUFFER

M 2P A

M 3P

Ib

V o

Ib

M 1N B M 2N

3N

[Peluso00] V.Peluso, P. Vancorenland, A.M.Marques, M.S.J.Steyaert, W.Sansen, A 900mV low-power A/D converter with 77dB dynamic range, IEEE J.Solid-State Circuits, vol. 35, no. 4, pp. 632-636, April 2000.

[Carvajal02] R.G.Carvajal, A. Torralba, J.Ramrez-Angulo, J.Tombs, F. Muoz, Compact low-power high slew-rate CMOS buffer for large capacitive loads, Electron. Lett., vol.38, no. 32, pp. 1348-1349, Oct. 2002. Antonio Torralba, Texas A&M, College Station, June 2004 21

4. FVF-NPD Applications
CLASS-AB OUTPUT BUFFER
M

2 V supply, 10pF capacitor load, 250 KHz input signal

Output transistor Output voltage current (A) (V)

2P

A M 1P

3P

Ib

Ib

M1N B M

3N

time (s)
[Carrillo04] J.M.Carrilo R.G.Carvajal,, A. Torralba, J.DuqueCarrillo, Rail-to-rail, low-power high slew-rate CMOS analog buffer, Electron. Lett., vol.40, no. 14, July 2004.

2N

More than 100uA max. output current with 30uA total quiescent current ! Antonio Torralba, Texas A&M, College Station, June 2004 22

4.FVF-NPD Applications
Biasing STAGE CLASS-AB OUTPUT STAGE
1 M3p 50/1 25/1 X M1p M2p 25/1 W :

M outp 500/1

I M outp

2-STAGE AMPLIFIER

VAB

+ -

Io 3,75 uA

+ -

VAB

Vout
I dp = 100 uA

3,75 uA Io

VV+
M in1 500/1 M in2 500/1

Rc

Cc V out

Y 8/1

M1n

M2n 8/1

I M outn

Output Stage (figure 13a)

M3n 16.5/1 1 :

M outn

165/1

a)

[Torralba00] A. Torralba, R.G.Carvajal, J. Martnez-Heredia, J.Ramrez-Angulo, Class-AB output stage for low voltage CMOS op-amps with accurate quiescent current control, Electron. Lett., vol.36, no. 21, pp. 1753-1754, Oct. 2000. Antonio Torralba, Texas A&M, College Station, June 2004 23

4.FVF Applications
CLASS-AB OUTPUT STAGE in a 2-STAGE OP-AMP
DC Gain Phase Margin Unity Gain frequency Quiescent output current Minimum current through output transistors Supply current PSRR dB deg (o) MHz (A) (A) (A) dB dB dB nV2/Hz V/s A 65 75 15 76 38 218 38 45 65 21 10 500

Unitary feedback

CMRR THD (1kHz) Input referred noise (100kHz) Slew Rate * (@ 0.3 V peak) Peak output current * (@ 0.3 V peak)

Non-inverting Gain= 5 with 2 internal resistors Antonio Torralba, Texas A&M, College Station, June 2004

VDD=1.5 V, C L=10pF, 0.8 m CMOS (Vt 0.85 V) Op-amp comp. CC=10pF, R C=500

24

3.FVF Structures. Summary

Current sensor (FVF-CS) Non-Symmetrical Class-AB Differential Pair (FVF-NDP)

0
;

,'

,E

,'

Symmetrical Class-AB Symmetrical Class-AB Pseudo Symmetrical Class-AB Pseudo Differential Pair (FVF-PDP) Differential Pair (FVF-SDP) Differential Pair (FVF-PDP)
Antonio Torralba, Texas A&M, College Station, June 2004

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4.FVF-PDP Applications
Symmetrical Class-AB Pesudo-Differential Pair (FVF-PDP)
CLASS-AB LINEAR MULTIPLIERS

[Ramirez-Angulo00] J.Ramrez-Angulo, R.G.Carvajal, J.M.Martnez-Heredia, 1.4V supply, wide swing, high frequency CMOS analogue multiplier with high current efficiency, Proc. ISCAS, vol. 5, pp. 533-536, 2000 [Ramirez-Angulo03] J.Ramrez-Angulo, S.Thoutam, A.Lpez-Martn, R.G.Carvajal, Low voltage CMOS analogue four quadrant multiplier based on Flipped-Voltage-Followers, Electron. Lett., vol.39, no. 25, Dec. 2003. Antonio Torralba, Texas A&M, College Station, June 2004

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4.FVF-PDP Applications
NON-LINEAR CLASS_AB TRANSCONDUCTORS
V DD 30 1 V CM MCM M op 30 1 Vcasp 30 1 30 1 30 1 30 1 30 1 M op+ 30 1 Vcasp M4 45 1 Vcasp 30 1 45 1 V b M2 V i+ Vo+ Vcasp M cas 30 1 MCM VCM

M cas

45 1 Vo Vi M1 M 3

45 1

10 1 M cas 10 1 VCMc MCMc M on 10 1 V casn 10 1 Vcasn

10 1

I b =1u

10 1 V casn 10 1

10 1 V casn 10 1 M on+ M cas 10 1 MCMc V CMc

10 1

10 1

V SS

[Carvajal02] R.G.Carvajal, J.Galn, J.Ramrez-Angulo, A. Torralba, Low-power, low voltage differential class-AB OTAs for SC circuits, Electron. Lett., vol.38, no. 22, pp. 1304-1305, Oct. 2002. [Galan02] J.Galn, A.P. VegaLeal, F. Muoz, R.G.Carvajal, A.Torralba, J.Tombs, J. Ramrez-Angulo, A 1.1V very low-power SD modulator for 14-b 16 KHz A/D conversion using a novel class AB transconductance amplifier, Proc. ISCAS, vol. 2, pp. 616-619, 2002. Antonio Torralba, Texas A&M, College Station, June 2004 27

4. FVF-PDP Applications
1.1 V, SC Integrator. 1pF capacitor load, 2MHz switching frequency
Output transistor Current ( A ) Differential Voltage (V)

time (s)
10 V/usec SR with only 11 uA total quiescent current ! (0.35 m CMOS)
Antonio Torralba, Texas A&M, College Station, June 2004

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4.FVF-PDP Applications
(Va - Vb) fo C1 Vin+ Vin+ + _ + + C2 + _ + Vo+

gm1
_ _ +

gm2
_ _

gm3
_ +

gm4
_ Vo -

C1

C2

gm-C Filter

CMFB1

CMFB2

gm5
_ _

(Va - Vb) Q

Antonio Torralba, Texas A&M, College Station, June 2004

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4.FVF-PDP Applications
gm-C Filter
Power supply Technology Chip area Frequency tuning range Q range (@10.7MHz) Vo,CM variation in the entire tuning range Power consumption range THD (@10.7MHz) SNR IM3 (@10.7MHz) IIP3 PSRR (@ 10.7 MHz) CMRR (@ 10.7 MHz) 2V 0.8 m CMOS 1.44 mm2 300 kHz- 32 MHz 4- 501 14 mV 1.18- 1.8 mW - 40dB@200 mVpp 45 dB 46 dB 8 dBm 39 dB 42 dB

Antonio Torralba, Texas A&M, College Station, June 2004

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4.FVF-PDP Applications
gm-C VCO
850 750 650 550 450 350 250 150 250

Amplitude (mVpp)

260

270

280

290

300

310

V tuning (Gm3) (mV)

[Galan03] J.Galn, R.G.Carvajal, F. Muoz, A.Torralba, J. Ramrez-Angulo, A low-power lowvoltage OTA-C sinusoidal oscillator with more than two decades of linear tuning range, Proc. ISCAS, vol. 1, pp. 677-680, 2003. [Galn04] J. Galan, R. G. Carvajal, A. Torralba, F. Muoz, and J. Ramirez-Angulo, A low-power, lowvoltage OTA-C simusoidal oscillator with a large tuning range. IEEE Trans. On CAS-II. (to appear) Antonio Torralba, Texas A&M, College Station, June 2004

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4.FVF Applications
Symmetrical Class-AB Pseudo-Differential Pair (FVF-PDP) gm-C VCO
Power supply 2V

Chip area

0.63 mm2 0.8 m

Technology

Vtuning control Frequency tuning range

25 mV- 500 mV

1 MHz- 25 MHz

Power consumption range

1.05- 1.58 mW

THD (2 / 25 MHz) @200 mVpp Phase Noise at 10kHz offset

1.12% / 0.66%

- 67 dBc/Hz

Antonio Torralba, Texas A&M, College Station, June 2004

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3.FVF Structures. Summary

Current sensor (FVF-CS) Non-Symmetrical Class-AB Differential Pair (FVF-NDP)

Symmetrical Class-AB Differential Pair (FVF-SDP) Symmetrical Class-AB Pseudo Differential Pair (FVF-PDP) Symmetrical Class-AB Differential Pair (FVF-SDP)

Antonio Torralba, Texas A&M, College Station, June 2004

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4.FVF-SDP Applications
Symmetrical Class-AB Differential Pair (FVF-SDP)
SUPER CLASS_AB TRANSCONDUCTORS 0.5 CMOS, V DD = 2 V, C L = 80pF 2 MHz square input signal

Quiescent power consumption = 120 uW SR = 78 V/us, 1% settling time = 110 ns THD (@100 kHz) = 0.15 %

[Baswa04] S. Baswa, A. Lpez-Martn, R.G.Carvajal, J.Ramrez-Angulo, Low voltage micro-power super classAB CMOS OTA, Electron. Lett., vol.40, no. 4, Feb. 2004. Antonio Torralba, Texas A&M, College Station, June 2004

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4.Other Applications
Translinear loops, Geometric Mean, Square-Root Domain Filters, etc.

A.J. Lpez-Martn and A. Carlosena, Current-mode multiplier/divider circuits based on the MOS translinear principle, Analog Integrated Circuits and Signal Processing, vol. 28, no. 3, pp. 265-278, 2001. A.J. Lpez-Martn and A. Carlosena, Systematic design of companding systems by component substitution, Analog Integrated Circuits and Signal Processing, vol. 28, no. 1, pp. 91-106, 2001. A.J. Lpez-Martn and A. Carlosena, A 3.3V CMOS RMS-DC converter based on the MOS Translinear principle, VLSI Design, 2002 Antonio Torralba, Texas A&M, College Station, June 2004 35

Conclusions
1. A new cell, called Flipped Voltage Follower (FVF) has been identified. 2. For low-voltage, low power, class AB operation. 3. Different applications have been reviewed (current mirror, voltage buffer, mixer, OTA, transconductance multiplier and op-amp output stage, filters, VCO, SD modulators). 4. Simulation and experimental results have been presented that show the potential of the socalled FVF structure.
Antonio Torralba, Texas A&M, College Station, June 2004

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The End

Antonio Torralba, Texas A&M, College Station, June 2004

37

4. FVF-NPD Applications
CLASS-AB OUTPUT BUFFER

[Carrillo04] J.M.Carrilo R.G.Carvajal,, A. Torralba, J.DuqueCarrillo, Rail-to-rail, low-power high slew-rate CMOS analog buffer, Electron. Lett., vol.40, no. 14, July 2004. Antonio Torralba, Texas A&M, College Station, June 2004

38