Analog IC Design: Chủ đề 6: Amplifiers Differential Amplifiers

Analog IC Design
Chủ đề 6:
Amplifiers
Differential Amplifiers
Outline
• Simple Amplifiers
• Cascode Amplifiers
• Differential Amplifiers
Analog IC Design-FETEL-HCMUS 2
MOSFETs as Current Sources
NOTE:
• A MOSFET behaves as a current source when it is operating in the
saturation region.
• An NMOSFET draws current from a point to ground (“sinks current”),
whereas a PMOSFET draws current from VDD to a point (“sources
current”).
VGS can vary with VX, VY

Common-Source (CS) Stage:  = 0
Amplifier circuit Small-signal analysis circuit

for determining voltage gain, Av
Small-signal analysis circuit for

determining output resistance, Rout
W
Av = − g m RD = − 2 nCox I D RD
L
Rin = 
Rout = RD
Common-Source Stage:   0
• Channel-length modulation results in reduced small-signal voltage

gain and amplifier output resistance.
Small-signal analysis circuit Small-signal analysis circuit for

for determining voltage gain, Av determining output resistance, Rout
Av = − g m (RD || rO ) -gmrO: intrinsic gain
Rin = 
Rout = RD || rO
CS Gain Variation with L
• An ideal current source has infinite small-signal resistance.

→The largest Av is achieved with a current source as the load.
• Since  is inversely proportional to L, Av increases with (L)1/2

W
2 nCox I D
L 2 nCoxWL
Av = g m ro = 
I D ID
CS Stage with Current-Source Load
• Av= -gmRD. For large AV, increasing RD, but increasing load resistance limits
the output voltage swing. → practical approach: current source.
• This is advantageous because a current-source has a high output resistance
and can tolerate a small voltage drop across it.
• Recall that a PMOS can be used as a current source from VDD.
→ Use a PMOS as a load of an NMOS CS amplifier.
Av = − g m1 (rO1 || rO 2 )
Rout = rO1 || rO 2
PMOS CS Stage with NMOS Load
• An NMOS can be used as the load for a PMOS CS amplifier. The

voltage gain is the same as before.
Av = − g m 2 (rO1 || rO 2 )
Rout = rO1 || rO 2
CS Stage with Diode-Connected Load

including MOSFET output resistances
  0:
If  = 0 :  1 
Av = − g m1  || rO 2 || rO1 
1 (W / L )1  gm2 
Av = − g m1  =−
gm2 (W / L )2 Rout =
1
|| rO 2 || rO1
gm2
→ Av is lower, but it is less dependent on process parameters (n and Cox
and drain current (ID).
CS Stage with Diode-Connected PMOS Load
  0:
 1 
Av = − g m 2  || ro1 || ro 2 
 g m1 
1
Rout = || ro1 || ro 2
g m1
CS Stage with Degeneration
By inserting a resistor in series with the source, we “degenerate” the CS stage.
This topology will decrease the gain of the amplifier but improve other aspects,
such as linearity, and I/O impedance.
for determining voltage gain, Av
RD RD
If  = 0 : Av = − If   0 : Av = −
1 1 R
+ RS + RS + D
gm gm g m ro
Example of CS Stage with Degeneration
• A diode-connected device degenerates a CS stage.
RD
Av = −
1 1
+
g m1 g m 2
Rout of CS Stage with Degeneration
• Degeneration boosts the output impedance

Current flowing down through ro is

i X − g m v1 = i X − g m (− i X RS )
= i X + g mi X RS
v1 = −iX RS
rO (i X + g mi X RS ) + i X RS = v X
= rO (1 + g m RS ) + RS  rO + g m rO RS
vX
i X IC Design-FETEL-HCMUS
Analog 13
Output Impedance Examples
 1  1
Rout = rO1 1 + g m1  +
 gm2  gm2
Rout

 rO1 1 + g m1
1 
 Rout  g m1rO1rO 2 + rO1
 gm2 
When 1/gm is parallel with rO2, we The impedance that degenerates the CS
often just consider 1/gm. stage is rO, instead of 1/gm
Rout
Body effect and channel-length modulation are taken into account
Rout = [1 + (gm+ gmb)RS] ro + RS

= [1 + (gm+ gmb)ro] RS + ro
 (gm+ gmb)RS ro + ro =[1+ (gm+ gmb)RS]ro
Output resistance has increased by a factor of 1+ (gm+ gmb)RS
Voltage Gain, Av
with body effect and channel-length modulation
Vout − g m rO RD
=
Vin RD + RS + rO + ( g m + g mb ) RS rO
Degenerated by resistor RS
Gm of a circuit – Method 1 (to find Gm)
• Use large signal model. Transconductance of a circuit: Gm =  ID/ Vin
For CS Source degeneration
I D I D VGS
Gm = =
Vin VGS Vin
Since VGS = Vin − I D RS → VGS / Vin = 1 − RS I D / Vin
I D I D
→ Gm = (1 − RS )
Vin VGS
gm
→ Gm = gm of M1
1 + g m RS
g m RD
Av = −Gm RD = −
Analog IC Design-FETEL-HCMUS 1 + g m RS 17
Gm of a circuit – Method 2
• Use small signal model:
VX
I out = g mV1 − g mb V X −
rO
I out RS
= g m (Vin − I out RS ) + g mb (− I out RS ) −
rO
It follows that
I out g m rO
Gm = =
Vin RS + [1 + ( g m + g mb ) RS ]rO
Lemma
• In a linear circuit, the voltage gain is equal to –GmRout
• Where:
– Gm denotes the transconductance of the circuit when the output
is shorted to ground.
– Rout is the output resistance when the input voltage is set to zero.
• Ex. CS stage
Vout g m rO RD
=−
Vin RD + RS + rO + ( g m + g mb ) RS rO
Vout g m rO RD [ RS + rO + ( g m + g mb ) RS rO ]
=−
Vin RS + rO + ( g m + g mb ) RS rO RD + RS + rO + ( g m + g mb ) RS rO
Gm RD // [RS +ro + (gm+ gmb)RSro]
Common-Gate Stage
Diode-Connected MOSFETs
Diode-connected NMOS Diode-connected PMOS
1 1
RX = ro1 RY = ro 2
g m1 gm2
Small-signal analysis circuit Small-signal analysis circuit
• Note that the small-signal model of a PMOS is identical to that of an NMOS.
Summary of MOSFET Impedances
• Looking into the • Looking into the • Looking into the

gate, the drain, the source, the
impedance is impedance is ro impedance is 1/gm in
infinite (∞). if the gate and parallel with ro if the
source are (ac) gate and drain are
grounded. (ac) grounded.
Common-Gate Amplifier Stage
• An increase in Vin decreases VGS and hence decreases ID.

→ The voltage drop across RD decreases → Vout increases
→ The small-signal voltage gain (Av) is positive.
Av = g m RD
Operation in Saturation Region
• For M1 to operate in saturation, Vout cannot fall below Vb-VTH.

→ Trade-off between headroom and voltage gain.
ID
>Vb –VTH for saturation mode
Important point:
1 W
VDD −  nCox (Vb − Vin − VTH ) 2 RD = Vb − VTH
2 L
Small-Signal Behavior, Av
Vout ( g m + g mb )rO + 1
Av = = RD
Vin RD + RS + rO + ( g m + g mb )rO RS
Input Impedance
RDIX +rO[IX - (gm+gmb)VX]=VX
VX RD + rO
=
I X 1 + ( g m + g mb )rO
RD 1
Rin  +
( g m + g mb )rO ( g m + g mb )
Output Impedance
Rout = {[1 + (gm+ gmb)ro] RS + ro }// RD
Simplified Analysis
Assuming = 0 and neglecting body effect
Small-signal analysis circuit for Small-signal analysis circuit for

determining input resistance, Rin determining output resistance, Rout
=-vX
ix = - gmv1 = gmvx
Rin= vx/ix = 1/gm
1
Rin = Rout = RD
gm
CG Stage with Source Resistance
Small-signal equivalent
circuit seen at input 1
gm
vX = vin
1
RS +
gm
For  = 0:
vout vout v X 1 RD
=  = g m RD  Av =
vin v X vin g m RS + 1 1
+ RS
gm
When a source resistance is present, the voltage gain is equal to that of a
CS stage with degeneration, only positive.
CG Stage with Source Resistance (Cont.)
Rout = rO (1 + g m RS ) + RS = (1 + g m rO )RS + rO
• The output impedance of a CG stage with source resistance
is identical to that of CS stage with degeneration.
CG Stage with Gate Resistance
• For low signal frequencies, the gate conducts no current.

→ Gate resistance does not affect the gain or I/O
impedances.
CG Stage Example
Small-signal equivalent Small-signal equivalent
circuit seen at input circuit seen at output
1 1
g m1 g m 2 1  
vX = vin = vin R  g r  R 1  + rO1
1 1 1 + (g m1 + g m 2 )RS out1 m1 O1  S
gm2 
+ RS  
g m1 g m 2
vout v X g m1RD   1  
Av =  = Rout   g m1rO1  || RS  + rO1  || RD
v X vin 1 + (g m1 + g m 2 )RS   gm2  
Source Follower Stage
Source Follower Stage
Simplified Analysis
vout rO || RL
Av  = 1
vin 1 + r || R
O L
gm
determining voltage gain, Av Equivalent circuit
vout = g m v1 (ro RL )
vin = v1 + vout
= g m (vin − vout )(ro RL )
Rout of Source Follower
• The output impedance of a source follower is relatively
low, whereas the input impedance is infinite (at low
frequencies); thus, it is useful as a voltage buffer.
1 1
Rout = || rO || RL  || RL
gm gm
Detail Analysis (cont.)
IX – gmVX – gmbVX = 0
Rout = 1/(gm +gmb)
Eliminate body effect in PMOS version
Summary on Simple Amplifier Design
• A MOSFET amplifier circuit should be designed to

1. ensure that the MOSFET operates in the saturation region,
2. allow the desired level of DC current to flow, and
3. couple to a small-signal input source and to an output “load”.
→ Proper “DC biasing” is required!
(DC analysis using large-signal MOSFET model)
• Key amplifier parameters:

(AC analysis using small-signal MOSFET model)
– Voltage gain Av  vout/vin
– Input impedance Rin  impedance seen between the input node and
ground (with output terminal floating)
– Output impedance Rout  impedance seen between the output node and
ground (with input terminal grounded)
Summary of Basic Transistor Stages
FETEL 2021 39
Comparison of Simple Amplifier Topologies
With simplified analysis, taking comparison:
Common Source Common Gate Source Follower
• Large Av < 0 • Large Av > 0 • 0 < Av ≤ 1

- degraded by RS -degraded by RS
• Large Rin • Small Rin • Large Rin
- decreased by RS – determined by
– determined by biasing
circuitry biasing circuitry
• Rout  RD • Rout  RD • Small Rout

- decreased by RS
• ro decreases Av & Rout • ro decreases Av &

• ro decreases Av & Rout
but impedance seen Rout
but impedance seen
looking into the drain looking into the drain
can be “boosted” by can be “boosted” by
source degeneration source degeneration
Cascode Stage
(a combination of common source and common gate stage)
Cascode Stage
CG
CS
Vout > Vin –VTH1 + VGS2 – VTH2
Addition of M2 to the circuit reduces the output

voltage swing by at least the overdrive voltage of
M2.
Gain Calculation
Small Signal Analysis
Example: ID1 (=gm1Vin) is divided between RP and

Calculate the voltage gain of the circuit 1/(gm2+gmb2), the impedance seen looking
into the source of M2.
Output Impedance
Rout = 1 + ( g m 2 + g mb 2 )rO 2 rO1 + rO 2

Rout  ( g m 2 + g mb 2 )rO1rO 2
M2 boots the output impedance of M1 by a factor of (gm2+ gmb2)rO2
Cascode Stage with Current Source Load
|AV|=GmRout
= gm1rO1[(gm2+gmb2)rO2+1]
NMOS Cascode Amplifier with PMOS Cascode Load
A large load impedance can be

achieved by using a PMOS
cascode current source.
RoN  g m 2 rO 2 rO1
RoP  g m3rO 3rO 4
Rout = RoN || RoP
Av= -Gm Rout
|Av|  gm1[(gm2rO2rO1)||(gm3rO3rO4)]
Features of Cascode Amplifier
✓Output impedance increases

✓Intrinsic gain is squared
✓Shielding property: M2 “shields”
CG
M1 from voltage variation at the
output
CS
Folded Cascode
• Idea: Convert the input voltage to current and apply the result to a
common-gate stage.
• The input and cascode devices need not be of the same type.
Simple folded cascode With proper biasing NMOS input
Folded Cascode (cont.)
• Large-Signal Behavior
If Vin < Vin1 M1 enters the triode region and ID1=I1
• Small-Signal Behavior: similar to that of simple cascode.

Differential Amplifiers
Differential & Single-Ended Operation
• A single-ended signal is taken with respect to a fixed potential
(usually ground).
• A differential signal is taken between two nodes that have equal and
opposite signals with respect to a “common mode” voltage and also
equal impedances to a fixed potential (usually ground).
Advantages of Differential Circuits
• Rejection of common-mode disturbance: supply noise, etc.
Rejection of coupling & feed through from other sources
Advantages (cont.)
• Reduction of coupling to other circuits
With perfect symmetry, the

components coupled from CK and
~CK to the signal line cancel each
other.
Other advantages:
✓Maximum voltage swing almost twice that in single-
ended operation
✓Even-order distortion suppressed
✓Biasing is easier
Basic Differential Pair
Vin1 - Vin2 varies from - to +. If Vin1 << Vin2, M1 is
off, M2 is on, and ID2 = ISS. → Vout1 = VDD and
Vout2 = VDD - RDISS. As Vin1 is closer to Vin2, M1
gradually turns on, drawing a fraction of ISS from RD1
and hence lowering Vout1. Since ID1+ ID2= ISS, the
drain current of M2 decreases and Vout2 rises. If Vin1 =
Vin2 → Vout1= Vout2= VDD- RDISS/2 which is the output
Common Mode level
Vout,CM
Common-Mode Behavior
Equivalent circuit if M3
operates in deep triode region
Common-Mode Behavior (Cont.)
• The lower limit of Vin,CM:
Vin,CM  VGS1 +(VGS3-VTH3) = 2VON +VTH
• Upper limit for Vin,CM:

– As Vin,CM starts approaching VDD at certain value of Vin,CM, M1 and
M2 come out of saturation. This happens at:
Vout1 + VTH= VDD –RDISS/2 +VTH
• In summary, Vin,CM is bounded as follows:
VGS1 +(VGS3-VTH3) = 2VON +VTH  Vin,CM  VDD –RDISS/2 +VTH
Input CM level of 1.6 V. If ISS = 0.5mA,
VTH = 0.5V, and VDD = 1.8V RD <?
Output Voltage Swing
• How large can the output voltage swings?
For M1 and M2 to be saturated, each output can go as high as VDD but as low as
approximately Vin,CM - VTH → The higher the input CM level, the smaller the
allowable output swings. For this reason, it is desirable to choose a relatively
low Vin,CM.
Differential pairs: Large Signal Analysis
Large Signal Analysis
=  n Cox (Vin1 − V in 2 )
1 W 4 I SS
I D1 − I D 2 − (Vin1 − Vin2 )
2
2 L W
 n Cox
L
As Vin exceeds a limit, one transistor carries the
entire ISS, turning off the other. Denoting this
value by Vin1.
59
Differential pairs: Small-Signal Analysis
• Method I: treat circuit as cascade of two stages and use
superposition.
For VX
Viewed as a CS stage degenerated by M2 Equivalent circuit
For VY
Replacing M1 by a
Thevenin equivalent Analog IC Design-FETEL-HCMUS 60
Small-Signal Analysis (Cont.)
VX − RD VY RD
= =
Vin1 1 1 Vin1 1 1
+ +
g m1 g m 2 g m1 g m 2
− 2 RD
(VX − VY ) |Due to Vin1 = Vin1
1 1
+
g m1 g m 2
(VX - VY)|Due to Vin1= - gmRDVin1 (for gm=gm1=gm2)
(identical, except a change

(VX - VY)|Due to Vin2= gmRDVin2 in the polarities)
(VX − VY )tot
= − g m RD
Vin1 − Vin 2
W
g m = 2 nCox ID
L
W
g m =  nCox (VGS − VTH )
L
2I D
gm =
VGS − VTH
“Half Circuit”
• Method II: If the circuit is perfectly symmetric and Vin1 and Vin2
change by equal and opposite amounts from equilibrium, then we
can use the concept of “half circuit.”
• Lemma: In the following symmetric circuit, if Vin1 changes from Vo to
Vo+V and Vin2 changes from V0 to V0-V, then VP does not change.
From another point of view, one transistor wants to pull VP up while the
other wants to pull it down. → VP can be grounded.
Slide 21
Small-Signal Analysis (Cont.)
• What if Vin1 and Vin2 are not
exactly differential?
→ Use superposition to find
the effect of differential
and common-mode
signals.
How much do VX and VY change as Vin,CM changes? If the circuit is fully symmetric and ISS
an ideal current source, the currents drawn by M1 and M2 from RD1 and RD2 are exactly
equal to ISS/2 and independent of Vin,CM. Thus, VX and VY remain equal to VDD - RD(ISS/2)
and experience no change as Vin,CM varies. Interestingly, the circuit simply amplifies the
difference between Vin1 and Vin2 while eliminating the effect of Vin,CM.
Common-Mode Response
• Symmetric Circuit
VX remains equal to VY
Common-Mode Response (Cont.)
• Asymmetric Circuit Effect of load resistance mismatch:
A common-mode change at the input

introduces a differential component at
the output.
Common mode(CM) to differential mode (DM) ACM-DM

75
Common-Mode Response (Cont.)
Effect of mismatches between
M1 and M2:
g m RD
ACM − DM = −
( g m1 + g m 2 ) RSS + 1
(Common-mode to diff-mode conversion)
Common Mode Rejection Ratio (CMRR)
• CMRR is a measure of differential amplifier which indicates its
ability to suppress common mode gain and enhance the
differential mode gain.
ADM
CMRR =
ACM − DM
RD
For mismatch in RD, ACM − DM = −
2 RSS
g m RD
For mismatch in gm, ACM − DM =−
( g m1 + g m 2 ) RSS + 1
If considering gm mismatch only,
where gm=(gm1+gm2)/2
Differential Pair with MOS Loads
Diode-connected Current source
Av = -gmN (g-1mP || rON || rOP) Av = − g m N (rON rOP )

 -gmN / gmP
 n (W / L) N (VGS − VTH ) P
Av = − =−
 p (W / L) P (VGS − VTH ) N
Resistance is eliminated
But the gain is limited by gmP
and trade-off between gain and swing
Exercise
Design of a CMOS Differential Amplifier with a Current
Mirror Load. → Submit and present on Dec 16. Group of 4
students.
Constraints Specifications
Small-signal gain: 200V/V
Frequency response
Power supply
(CL=10pF): f-3dB=100kHz
Technology: 180nm
ICMR: 0.8V→1.4V
Temperature
Slew rate (CL=10pF): 10V/us
Power dissipation: <3mW
https://aicdesign.org/wp-content/uploads/2018/08/lecture19-150211.pdf
Exercise
Design of a CMOS Unbuffer Opamp. → Submit and present: 30/12.

Analog IC Design: Chủ đề 6: Amplifiers Differential Amplifiers

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Analog IC Design

VGS can vary with VX, VY

Amplifier circuit Small-signal analysis circuit

Small-signal analysis circuit for

• Channel-length modulation results in reduced small-signal voltage

Small-signal analysis circuit Small-signal analysis circuit for

Av = − g m (RD || rO ) -gmrO: intrinsic gain

• An ideal current source has infinite small-signal resistance.

• Since  is inversely proportional to L, Av increases with (L)1/2

• An NMOS can be used as the load for a PMOS CS amplifier. The

Amplifier circuit Small-signal analysis circuit

• A diode-connected device degenerates a CS stage.

• Degeneration boosts the output impedance

Small-signal analysis circuit for

Current flowing down through ro is

Rout = [1 + (gm+ gmb)RS] ro + RS

Output resistance has increased by a factor of 1+ (gm+ gmb)RS

For CS Source degeneration

Gm RD // [RS +ro + (gm+ gmb)RSro]

Diode-connected NMOS Diode-connected PMOS

Small-signal analysis circuit Small-signal analysis circuit

• Note that the small-signal model of a PMOS is identical to that of an NMOS.

• Looking into the • Looking into the • Looking into the

• An increase in Vin decreases VGS and hence decreases ID.

• For M1 to operate in saturation, Vout cannot fall below Vb-VTH.

>Vb –VTH for saturation mode

RDIX +rO[IX - (gm+gmb)VX]=VX

Rout = {[1 + (gm+ gmb)ro] RS + ro }// RD

Small-signal analysis circuit for Small-signal analysis circuit for

• For low signal frequencies, the gate conducts no current.

• A MOSFET amplifier circuit should be designed to

• Key amplifier parameters:

Common Source Common Gate Source Follower

• Large Av < 0 • Large Av > 0 • 0 < Av ≤ 1

• Rout  RD • Rout  RD • Small Rout

• ro decreases Av & Rout • ro decreases Av &

Addition of M2 to the circuit reduces the output

Example: ID1 (=gm1Vin) is divided between RP and

Rout = 1 + ( g m 2 + g mb 2 )rO 2 rO1 + rO 2

A large load impedance can be

✓Output impedance increases

Simple folded cascode With proper biasing NMOS input

If Vin < Vin1 M1 enters the triode region and ID1=I1

• Small-Signal Behavior: similar to that of simple cascode.

Rejection of coupling & feed through from other sources

With perfect symmetry, the

• Upper limit for Vin,CM:

Viewed as a CS stage degenerated by M2 Equivalent circuit

(VX - VY)|Due to Vin1= - gmRDVin1 (for gm=gm1=gm2)

(identical, except a change

A common-mode change at the input

Common mode(CM) to differential mode (DM) ACM-DM

If considering gm mismatch only,

Av = -gmN (g-1mP || rON || rOP) Av = − g m N (rON rOP )

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