Tutorial Sheet DM-2 (07.11.

2023)
𝑊 𝑊 𝑊 𝑊
1. Design the circuit shown in Fig. 1 to obtain IOUT1 = 10 mA. Given, ( ) ⁄( ) = 20, ( ) ⁄( ) =
𝐿 2 𝐿 1 𝐿 1 𝐿 3
𝑊 𝑊 𝑊 𝑊
5, ( ) ⁄( ) = 10, 𝐾𝑛′ ( ) = 1 mA/V2, 𝑉𝑡ℎ𝑛 = |𝑉𝑡ℎ𝑝 | = 1 V, and λ𝑛 = |λ𝑝 | = 0, where ( ) is
𝐿 5 𝐿 4 𝐿 1 𝐿 𝑥
the ratio of width to length of the transistor 𝑀𝑥 (x = 1, 2, 3, 4, 5). Assume, VDD = 12 V.
a) What is the voltage at the gates of M1 and M2?
b) Find the required value for R.
c) What is the lowest voltage VOUT1 allowed at the drain of M2 while M2 remains in the saturation
region?
d) Find the values of IM3 and IOUT2.
e) Considering M4 and M5 have equal gate length of 0.5 µm, find M5 width W5 for W4 = 5 µm.
f) Keeping the gate length same, if the M3 width W3 is made 3 times of the earlier value, what are the
new values of IM3 and IOUT2?

[Ans: a) 𝑉𝐺𝑆 = 2 V; b) R = 20 kΩ; c) Minimum 𝑉𝑂𝑈𝑇1 = 1 V; d) 𝐼𝑀3 = 0.1 mA, 𝐼𝑂𝑈𝑇2= 1 mA; e) 𝑊5 =
50 µm; f) 𝐼𝑀3 = 0.3 mA, 𝐼𝑂𝑈𝑇2= 3 mA]

Fig. 1

2. For the circuits shown in Fig. 2(a) and 2(b), 𝑅1 = 75 kΩ, 𝑅2 = 20 kΩ, 𝑅𝐶 = 4.0 kΩ, 𝑅𝐸1 = 0.2 kΩ,
𝑅𝐸2 = 1.0 kΩ, 𝑉𝐶𝐶 = 12 V. Device Q1 has 𝜏𝐹 = 15 ps, 𝐶𝑗𝑒0 = 50 fF, 𝐶𝜇0 = 50 fF, 𝑉0𝑒 = 0.6 V, 𝑉0𝑐 = 0.6
V. Assume, β = 120, 𝑉𝐵𝐸 = 0.7 V, 𝑉𝑇 = 26 mV @ 27oC, 𝑉𝐴 = ∞, V𝐶𝐸𝑠𝑎𝑡 = 0.4 V.
Part A:
a) Find 𝐶𝑑𝑒 , 𝐶𝑗𝑒 , 𝐶𝜋 , 𝐶𝜇 and 𝑓𝑇 for the BJT Q1.

[Ans: a) 𝐶𝑑𝑒 = 0.785 pF, 𝐶𝑗𝑒 = 100 fF, 𝐶𝜋 = 0.885 pF, 𝐶𝜇 = 17.659 fF, 𝑓𝑇 = 9.22 GHz]

Part B:
The circuit is driven by a signal source (𝑣𝑠𝑖𝑔 ) having internal resistance of 𝑅𝑠𝑖𝑔 = 10 kΩ, the signal
output is taken across a load resistance of 𝑅𝐿 = 15 kΩ as shown in Fig. 2(a). The values of capacitors
𝐶𝐶1 , 𝐶𝐶2 , 𝐶𝐸1 , and 𝐶𝐸2 are large enough to provide negligible voltage drop across them at the operating
frequency range.
a) Find the values of open-circuit voltage gain (𝐴𝑣0 = 𝑣𝑜 ⁄𝑣𝑖 ), input resistance (𝑅𝑖 ), and output
resistance (𝑅𝑜 ).
(b) Calculate the values of input resistance (𝑅𝑖𝑛 ), output resistance (𝑅𝑜𝑢𝑡 ), and voltage gain (𝐴𝑣 =
𝑣𝑜 ⁄𝑣𝑖 ) with 𝑅𝐿 .
c) Determine the overall voltage gain (𝐺𝑣 = 𝑣𝑜 ⁄𝑣𝑠𝑖𝑔 ).
d) Find the high frequency pole frequencies using Miller’s theorem.
e) If the capacitor 𝐶𝐸1 is removed (i.e. 𝐶𝐸1 = 0), find the values of 𝐴𝑣0 , 𝑅𝑖 , 𝑅𝑜 , 𝑅𝑖𝑛 , 𝑅𝑜𝑢𝑡 , 𝐴𝑣 , and 𝐺𝑣 .
[Ans: a) 𝐴𝑣0 = -209.384 V/V, 𝑅𝑖 = 2.292 kΩ, 𝑅𝑜 = 4 kΩ;
b) 𝐴𝑣 = -165.309 V/V, 𝑅𝑖𝑛 = 2.001 kΩ, 𝑅𝑜𝑢𝑡 = 3.158 kΩ;
c) 𝐺𝑣 = -27.563 V/V;
d) 𝑓𝑝1 = 24.975 MHz, 𝑓𝑝2 = 2.837 GHz;
e) 𝐴𝑣0 = -18.123 V/V, 𝑅𝑖 = 26.492 kΩ, 𝑅𝑜 = 4 kΩ, 𝐴𝑣 = -14.308 V/V, 𝑅𝑖𝑛 = 9.893 kΩ, 𝑅𝑜𝑢𝑡 = 3.158
kΩ, 𝐺𝑣 = -7.116 V/V]

VCC

RC Rout
CC2
R1
Rin
CC1 Vo
Q1 Ro RL
Ri
Rsig Vi RE1 CE1
R2
Vsig
RE2 CE2

Fig. 2(a)

Part C:
For the circuit shown in Fig. 2(b), 𝑅𝑠𝑖𝑔 = 10 kΩ, 𝑅𝐿 = 15 kΩ, and the values of 𝐶𝐶1 , 𝐶𝐶2 and 𝐶𝐵 are
large enough to provide negligible voltage drop across them at the operating frequency range.
a) Find the values of open-circuit voltage gain (𝐴𝑣0 = 𝑣𝑜 ⁄𝑣𝑖 ), input resistance (𝑅𝑖 ), and output
resistance (𝑅𝑜 ).
(b) Calculate the values of input resistance (𝑅𝑖𝑛 ), output resistance (𝑅𝑜𝑢𝑡 ), and voltage gain (𝐴𝑣 =
𝑣𝑜 ⁄𝑣𝑖 ) with 𝑅𝐿 .
c) Determine the overall voltage gain (𝐺𝑣 = 𝑣𝑜 ⁄𝑣𝑠𝑖𝑔 ).
d) Find the high frequency pole frequencies.

[Ans: a) 𝐴𝑣0 = 209.384 V/V, 𝑅𝑖 = 18.951 Ω, 𝑅𝑜 = 4 kΩ;

b) 𝐴𝑣 = 165.309 V/V, 𝑅𝑖𝑛 = 18.656 Ω, 𝑅𝑜𝑢𝑡 = 3.158 kΩ;
c) 𝐺𝑣 = 0.308 V/V;
d) 𝑓𝑝1 = 9.658 GHz, 𝑓𝑝2 = 2.854 GHz]
 VCC

RC Rout
CC2
R1
CB
Q1 Ro Vo
RL
Rin
CC1 Ri
Rsig
Vsig Vi R2 RE1

RE2

Fig. 2(b)

3. For the circuit shown in Fig. 3(a) and (b), 𝑅1 = 70 kΩ, 𝑅2 = 30 kΩ, 𝑅𝐷 = 4.0 kΩ, 𝑅𝑆1 = 0.2 kΩ, 𝑅𝑆2
= 1.0 kΩ, 𝑉𝐷𝐷 = 12 V. MOSFET M1 has 𝐶𝑔𝑠 = 0.9 pF, and 𝐶𝑔𝑑 = 0.4 pF. Assume, 𝑘𝑛 = 2.0 mA/V2,
𝑉𝑡ℎ𝑛 = 0.8 V, 𝜆 = 0.
Part A:
The circuit is driven by a signal source (𝑣𝑠𝑖𝑔 ) having internal resistance of 𝑅𝑠𝑖𝑔 = 10 kΩ, the signal
output is taken across a load resistance of 𝑅𝐿 = 15 kΩ as shown in Fig. 3(a). The values of capacitors
𝐶𝐶1 , 𝐶𝐶2 𝐶𝑆1 , and 𝐶𝑆2 are large enough to provide negligible voltage drop across them at the operating
frequency range.
a) Find the values of open-circuit voltage gain (𝐴𝑣0 = 𝑣𝑜 ⁄𝑣𝑖 ), input resistance (𝑅𝑖 ), and output
resistance (𝑅𝑜 ).
(b) Calculate the values of input resistance (𝑅𝑖𝑛 ), output resistance (𝑅𝑜𝑢𝑡 ), and voltage gain (𝐴𝑣 =
𝑣𝑜 ⁄𝑣𝑖 ) with 𝑅𝐿 .
c) Determine the overall voltage gain (𝐺𝑣 = 𝑣𝑜 ⁄𝑣𝑠𝑖𝑔 ).
d) Find the high frequency pole frequencies using Miller’s theorem.
e) If the capacitor 𝐶𝑆1 is removed (i.e. 𝐶𝑆1 = 0), find the values of 𝐴𝑣0 , 𝑅𝑖 , 𝑅𝑜 , 𝑅𝑖𝑛 , 𝑅𝑜𝑢𝑡 , 𝐴𝑣 and 𝐺𝑣 .
[Ans: a) 𝐴𝑣0 = -9.336 V/V, 𝑅𝑖 = ∞, 𝑅𝑜 = 4 kΩ;
b) 𝐴𝑣 = -7.371 V/V, 𝑅𝑖𝑛 = 21 kΩ, 𝑅𝑜𝑢𝑡 = 3.158 kΩ;
c) 𝐺𝑣 = -4.993 V/V;
d) 𝑓𝑝1 = 5.531 MHz, 𝑓𝑝2 = 111.007 MHz;
e) 𝐴𝑣0 = -6.365 V/V, 𝑅𝑖 = ∞, 𝑅𝑜 = 4 kΩ, 𝐴𝑣 = -5.025 V/V, 𝑅𝑖𝑛 = 21 kΩ, 𝑅𝑜𝑢𝑡 = 3.158 kΩ, 𝐺𝑣 = -3.404
V/V]
 VDD

RD Rout
CC2
R1
Rin
CC1 Vo
M 1 Ro RL
Ri
Rsig Vi
R2 RS1 CS1
Vsig
RS2 CS2

Fig. 3(a)

Part B:
For the circuit shown in Fig. 3(b), 𝑅𝑠𝑖𝑔 = 10 kΩ, 𝑅𝐿 = 15 kΩ, and the values of 𝐶𝐶1 and 𝐶𝐶2 are large
enough to provide negligible voltage drop across them at the operating frequency range.
a) Find the values of open-circuit voltage gain (𝐴𝑣0 = 𝑣𝑜 ⁄𝑣𝑖 ), input resistance (𝑅𝑖 ), and output
resistance (𝑅𝑜 ).
b) Calculate the values of input resistance (𝑅𝑖𝑛 ), output resistance (𝑅𝑜𝑢𝑡 ), and voltage gain (𝐴𝑣 =
𝑣𝑜 ⁄𝑣𝑖 ) with 𝑅𝐿 .
c) Determine the overall voltage gain (𝐺𝑣 = 𝑣𝑜 ⁄𝑣𝑠𝑖𝑔 ).
d) Find the high frequency pole frequencies.

[Ans: a) 𝐴𝑣0 = 9.336 V/V, 𝑅𝑖 = 428.449 Ω, 𝑅𝑜 = 4 kΩ;

b) 𝐴𝑣 = 7.371 V/V, 𝑅𝑖𝑛 = 315.723 Ω, 𝑅𝑜𝑢𝑡 = 3.158 kΩ;
c) 𝐺𝑣 = 0.226 V/V;
d) 𝑓𝑝1 = 577.791 MHz, 𝑓𝑝2 = 125.993 MHz]

VDD

RD Rout
CC2
R1
CG

M 1 Ro Vo
RL
Rin
CC1 Ri
Rsig
Vsig Vi R2 R
S1

RS2

Fig. 3(b)