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  • Hardware Tutorial 04

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    Taqi Shah
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    The document discusses timing in logic circuits. It provides: 1. A circuit diagram and asks to construct a truth table to determine its function. 2. A timing diagram showing the time delay of 2ns for a two input NAND gate. 3. Removing a spike from the timing diagram by redrawing the circuit to include inverters with a time delay of 1ns. It asks if this solution would still work if the inverters had a delay of 0.95ns instead. 4. A physics-based transistor model and charging capacitor equation, asking which of two 8-way buffer circuits would be faster based on this model.

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    The document discusses timing in logic circuits. It provides: 1. A circuit diagram and asks to construct a truth table to determine its function. 2. A timing diagram showing the time delay of 2ns for a two input NAND gate. 3. Removing a spike from the timing diagram by redrawing the circuit to include inverters with a time delay of 1ns. It asks if this solution would still work if the inverters had a delay of 0.95ns instead. 4. A physics-based transistor model and charging capacitor equation, asking which of two 8-way buffer circuits would be faster based on this model.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
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    13 views2 pages

    Hardware Tutorial 04

    Uploaded by

    Taqi Shah
    The document discusses timing in logic circuits. It provides: 1. A circuit diagram and asks to construct a truth table to determine its function. 2. A timing diagram showing the time delay of 2ns for a two input NAND gate. 3. Removing a spike from the timing diagram by redrawing the circuit to include inverters with a time delay of 1ns. It asks if this solution would still work if the inverters had a delay of 0.95ns instead. 4. A physics-based transistor model and charging capacitor equation, asking which of two 8-way buffer circuits would be faster based on this model.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 2

    Tutorial 4: Timing in Logic Circuits

    Consider the following famous circuit:


    D X C E

    A B

    1. Using the simple switch model (ie Boolean Algebra) construct a truth table to determine its function. A 0 0 1 1 B 0 1 0 1 C D E X

    2. Now, assume the switch model has a time delay, and let the time delay for a two input NAND gate be 2ns (2*10-9 seconds). Complete the following timing diagram for the circuit: .
    A B C D E X 2 4 6 8 10 12 14

    Time (ns)

    DOC112: Hardware Tutorial 4

    Page 1

    3. Assuming that an inverter causes a time delay of 1ns re-draw the circuit to remove the spike. Would this solution work if the inverters had a time delay of 0.95 ns rather than 1ns.

    4. (A difficult problem for those geniuses who understand Physics)

    In our most complex model of the transistor we attributed the delay in switching a gate to the length of time it took to charge the capacitor between the gate and the drain. The input voltage to a gate is governed by the equation V = 5( 1- exp(-t/RC)).
    A

    Using this model, and assuming that 1. the input capacitances of all gates are the same 2. the gates all switch at about the same voltage level eg 1V for logic 1 determine which of the two implementations of an eight way buffer circuit will be the faster. . .

    DOC112: Hardware Tutorial 4

    Page 2

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