Asynchronous fifo

Hierarchical Architecture

Top Level Architecture

Coding
Top level
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity async is
Port ( wclk:
in STD_LOGIC;
rclk:
in STD_LOGIC;
winc:
in STD_LOGIC;
rinc:
in STD_LOGIC;
wrst_n:
in STD_LOGIC;
rrst_n:
in STD_LOGIC;
wdata:
in STD_LOGIC_vector(7 downto 0);
rdata:
out STD_LOGIC_vector(7 downto 0);
almost_wfull: out STD_LOGIC;
almost_rempty: out STD_LOGIC);

end async;
architecture behaviraol1 of async is
component sync_r2wreg is
rptr:

port( wq2_rptr: out std_logic_vector(4 downto 0);

in std_logic_vector(4 downto 0);
wclk: in std_logic;
wrst_n: in std_logic );

end component;
component sync_w2rreg is
port( rq2_wptr: out std_logic_vector(4 downto 0);
wptr: in std_logic_vector(4 downto 0);
rclk: in std_logic;
rrst_n: in std_logic );
end component;
component dpram is
port ( wclk: in std_logic;
waddr: in std_logic_vector (3 downto 0);
raddr: in std_logic_vector (3 downto 0);
wdata: in std_logic_vector(7 downto 0);
rdata: out std_logic_vector(7 downto 0);
wclken: in std_logic;
wfull: in std_logic;
rclk: in std_logic;
rinc: in std_logic;
rempty: in std_logic);
end component;
component rptr_empty is
port (rclk: in std_logic;
raddr: out std_logic_vector (3 downto 0);
rptr: out std_logic_vector (4 downto 0);
rempty: out std_logic;
rq2_wptr: in std_logic_vector(4 downto 0);
rinc: in std_logic;
rrst_n: in std_logic);

end component;
component wptr_full is
port( wclk: in std_logic;
waddr: out std_logic_vector (3 downto 0);
wptr: out std_logic_vector (4 downto 0);
wfull: out std_logic;
wq2_rptr: in std_logic_vector(4 downto 0);
winc: in std_logic;
wrst_n: in std_logic);
end component;
signal waddr: std_logic_vector(3 downto 0);
signal raddr: std_logic_vector(3 downto 0);
signal wptr: std_logic_vector(4 downto 0);
signal rptr: std_logic_vector(4 downto 0);
signal wq2_rptr: std_logic_vector(4 downto 0);
signal rq2_wptr: std_logic_vector(4 downto 0);
signal wfull1: STD_LOGIC;
signal rempty1: STD_LOGIC;
begin
almost_wfull <= wfull1;
almost_rempty <= rempty1;
F1: dpram port map ( wclk,waddr,raddr,wdata,rdata,winc,wfull1,rclk,rinc,rempty1 );
F2: wptr_full port map ( wclk,waddr,wptr,wfull1,wq2_rptr,winc,wrst_n );
F3: rptr_empty port map ( rclk,raddr,rptr,rempty1,rq2_wptr,rinc,rrst_n );
F4: sync_r2wreg port map ( wq2_rptr,rptr,wclk,wrst_n );
F5: sync_w2rreg port map ( rq2_wptr,wptr,rclk,rrst_n );
end behaviraol1;

Dual port Register file

Toplevel architecture

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity dpram is
port ( wclk: in std_logic;
waddr: in std_logic_vector (3 downto 0);
raddr: in std_logic_vector (3 downto 0);
wdata: in std_logic_vector(7 downto 0);
rdata: out std_logic_vector(7 downto 0);
wclken: in std_logic;
wfull: in std_logic;
rclk: in std_logic;
rinc: in std_logic;
rempty: in std_logic);
end dpram;
architecture a_dpram of dpram is
type ram_array is array (0 to 15 ) of std_logic_vector(7 downto 0);
signal ram: ram_array ;
begin
write : process(wclk)
begin
if (wclk'event and wclk = '1') then
if ( wfull='0'and wclken='1') then
ram( conv_integer(waddr))<=wdata;
end if;
end if;
end process;
read:process(rclk)
begin
if (rclk='1' and rclk'event) then
if (rinc = '1' and rempty ='0') then
rdata<=ram(conv_integer(raddr));
end if;
end if;

end process;
end a_dpram;

Empty Logic

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity rptr_empty is
port

(rclk: in std_logic;
raddr: out std_logic_vector (3 downto 0);
rptr: out std_logic_vector (4 downto 0);
rempty: out std_logic;
rq2_wptr: in std_logic_vector(4 downto 0);
rinc: in std_logic;
rrst_n: in std_logic);

end rptr_empty;
architecture behaviraol of rptr_empty is
signal rbin:
std_logic_vector (4 downto 0);
signal rbinnext: std_logic_vector (4 downto 0);
signal rgraynext: std_logic_vector (4 downto 0);
signal r_empty: std_logic;
signal r_empty1: std_logic;
begin
process(rclk,rrst_n)
begin
if(rclk'event and rclk='1') then
if(rrst_n='1') then
rbin<=(others=>'0');
rptr<=(others=>'0');
else
rbin<=rbinnext;
rptr<=rgraynext;
end if;
end if;
end process;
------ Gray counter--------rbinnext <= rbin + (rinc and (not r_empty1));
rgraynext <= ('0' & rbinnext(4 downto 1)) xor (rbinnext);
---Memory address counter ----------

raddr<=rbin(3 downto 0);

r_empty<='1' when (rgraynext=rq2_wptr) else '0';
rempty<=r_empty1;
process(rclk,rrst_n)
begin
if(rclk'event and rclk='1')then
if(rrst_n='1')then
r_empty1<='1';
else
r_empty1<=r_empty;
end if;
end if;
end process;

end behaviraol;

Full Logic

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity wptr_full is
port( wclk:

in std_logic;

waddr: out std_logic_vector (3 downto 0);

wptr: out std_logic_vector (4 downto 0);
wfull: out std_logic;
wq2_rptr: in std_logic_vector(4 downto 0);
winc: in std_logic;
wrst_n: in std_logic);
end wptr_full;
architecture behavioral of wptr_full is
signal wbin:
std_logic_vector (4 downto 0);
signal wbinnext:
std_logic_vector (4 downto 0);
signal wgraynext:
std_logic_vector (4 downto 0);
signal w_full,w_full1: std_logic;
begin
process(wclk,wrst_n)
begin
if(wclk'event and wclk='1') then
if(wrst_n='1') then
wbin<=(others=>'0');
wptr<=(others=>'0');
else
wbin<=wbinnext;
wptr<=wgraynext;
end if;
end if;
end process;
------ Gray counter--------wbinnext <= wbin + (winc and (not w_full1));
wgraynext <= ('0' & wbinnext(4 downto 1)) xor (wbinnext);
---Memory address counter ---------waddr <= wbin(3 downto 0);
w_full<= '1' when (wgraynext(4 downto 0)=(not wq2_rptr(4) & not wq2_rptr(3) &
wq2_rptr(2 downto 0)))
else '0';

process(wrst_n,wclk)
begin
if(wclk'event and wclk='1') then
if (wrst_n='1') then
w_full1<='0';
else
w_full1<=w_full;
end if;
end if;
end process;
wfull<=w_full1;
end behavioral;

Synchronizer for write operation

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sync_w2rreg is
port( rq2_wptr: out std_logic_vector(4 downto 0);
wptr: in std_logic_vector(4 downto 0);
rclk: in std_logic;
rrst_n: in std_logic );
end sync_w2rreg;

architecture Behavioral of sync_w2rreg is

signal rq1_wptr: std_logic_vector(4 downto 0);
begin
process(rclk,rrst_n)
begin
if (rclk'event and rclk = '1') then
if(rrst_n='1') then
rq2_wptr<=(others=>'0');
rq1_wptr<=(others=>'0');
else
rq2_wptr<=rq1_wptr;
rq1_wptr<=wptr;
end if;
end if;
end process;
end Behavioral;

Synchronizer for read operation

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sync_r2wreg is
port( wq2_rptr: out std_logic_vector(4 downto 0);
rptr: in std_logic_vector(4 downto 0);
wclk: in std_logic;
wrst_n: in std_logic );
end sync_r2wreg;

architecture Behavioral of sync_r2wreg is

signal wq1_rptr: std_logic_vector(4 downto 0);
begin
process(wclk,wrst_n)
begin
if (wclk'event and wclk = '1') then
if(wrst_n='1') then
wq2_rptr<=(others=>'0');
wq1_rptr<=(others=>'0');
else
wq2_rptr<=wq1_rptr;
wq1_rptr<=rptr;
end if;
end if;
end process;
end Behavioral;

Synthesis report
Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.33 s | Elapsed : 0.00 / 1.00 s
--> Reading design: async.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation

3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
7.1) Device utilization summary
7.2) TIMING REPORT
===============================================================
==========
*
Synthesis Options Summary
*
===============================================================
==========
---- Source Parameters
Input File Name
: "async.prj"
Input Format
: mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name
Output Format
Target Device

: "async"
: NGC
: xc2s50-5-pq208

---- Source Options

Top Module Name
: async
Automatic FSM Extraction
: YES
FSM Encoding Algorithm
: Auto
FSM Style
: lut
RAM Extraction
: Yes
RAM Style
: Auto
ROM Extraction
: Yes
ROM Style
: Auto
Mux Extraction
: YES
Decoder Extraction
: YES
Priority Encoder Extraction
: YES
Shift Register Extraction
: YES
Logical Shifter Extraction
: YES
XOR Collapsing
: YES
Resource Sharing
: YES
Multiplier Style
: lut
Automatic Register Balancing
: No
---- Target Options
Add IO Buffers

: YES

Global Maximum Fanout

: 100
Add Generic Clock Buffer(BUFG) : 4
Register Duplication
: YES
Equivalent register Removal
: YES
Slice Packing
: YES
Pack IO Registers into IOBs
: auto
---- General Options
Optimization Goal
: Speed
Optimization Effort
:1
Keep Hierarchy
: NO
Global Optimization
: AllClockNets
RTL Output
: Yes
Write Timing Constraints
: NO
Hierarchy Separator
:/
Bus Delimiter
: <>
Case Specifier
: maintain
Slice Utilization Ratio
: 100
Slice Utilization Ratio Delta
:5
---- Other Options
lso
: async.lso
Read Cores
: YES
cross_clock_analysis
: NO
verilog2001
: YES
safe_implementation
: No
Optimize Instantiated Primitives : NO
tristate2logic
: Yes
use_clock_enable
: Yes
use_sync_set
: Yes
use_sync_reset
: Yes
enable_auto_floorplanning
: No
===============================================================
==========
===============================================================
==========
*
HDL Compilation
*
===============================================================
==========
Compiling vhdl file "D:/async_fifo/dpram.vhd" in Library work.
Architecture a_dpram of Entity dpram is up to date.
Compiling vhdl file "D:/async_fifo/wptr_full.vhd" in Library work.
Entity <wptr_full> compiled.

Entity <wptr_full> (Architecture <behavioral>) compiled.

Compiling vhdl file "D:/async_fifo/rptr_empty.vhd" in Library work.
Entity <rptr_empty> compiled.
Entity <rptr_empty> (Architecture <behaviraol>) compiled.
Compiling vhdl file "D:/async_fifo/sync_r2wreg.vhd" in Library work.
Entity <sync_r2wreg> compiled.
Entity <sync_r2wreg> (Architecture <behavioral>) compiled.
Compiling vhdl file "D:/async_fifo/sync_w2rreg.vhd" in Library work.
Entity <sync_w2rreg> compiled.
Entity <sync_w2rreg> (Architecture <behavioral>) compiled.
Compiling vhdl file "D:/async_fifo/async_fif0.vhd" in Library work.
Architecture behaviraol1 of Entity async is up to date.
===============================================================
==========
*
HDL Analysis
*
===============================================================
==========
Analyzing Entity <async> (Architecture <behaviraol1>).
Entity <async> analyzed. Unit <async> generated.
Analyzing Entity <dpram> (Architecture <a_dpram>).
Entity <dpram> analyzed. Unit <dpram> generated.
Analyzing Entity <wptr_full> (Architecture <behavioral>).
Entity <wptr_full> analyzed. Unit <wptr_full> generated.
Analyzing Entity <rptr_empty> (Architecture <behaviraol>).
Entity <rptr_empty> analyzed. Unit <rptr_empty> generated.
Analyzing Entity <sync_r2wreg> (Architecture <behavioral>).
Entity <sync_r2wreg> analyzed. Unit <sync_r2wreg> generated.
Analyzing Entity <sync_w2rreg> (Architecture <behavioral>).
Entity <sync_w2rreg> analyzed. Unit <sync_w2rreg> generated.
===============================================================
==========
*
HDL Synthesis
*
===============================================================
==========
Synthesizing Unit <sync_w2rreg>.
Related source file is "D:/async_fifo/sync_w2rreg.vhd".
Found 5-bit register for signal <rq2_wptr>.

Found 5-bit register for signal <rq1_wptr>.

Summary:
inferred 10 D-type flip-flop(s).
Unit <sync_w2rreg> synthesized.
Synthesizing Unit <sync_r2wreg>.
Related source file is "D:/async_fifo/sync_r2wreg.vhd".
Found 5-bit register for signal <wq2_rptr>.
Found 5-bit register for signal <wq1_rptr>.
Summary:
inferred 10 D-type flip-flop(s).
Unit <sync_r2wreg> synthesized.
Synthesizing Unit <rptr_empty>.
Related source file is "D:/async_fifo/rptr_empty.vhd".
Found 5-bit register for signal <rptr>.
Found 1-bit xor2 for signal <$n0003> created at line 49.
Found 1-bit xor2 for signal <$n0004> created at line 49.
Found 1-bit xor2 for signal <$n0005> created at line 49.
Found 1-bit xor2 for signal <$n0006> created at line 49.
Found 5-bit comparator equal for signal <$n0008> created at line 54.
Found 1-bit register for signal <r_empty1>.
Found 5-bit register for signal <rbin>.
Found 5-bit adder for signal <rbinnext>.
Summary:
inferred 11 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
inferred 1 Comparator(s).
Unit <rptr_empty> synthesized.
Synthesizing Unit <wptr_full>.
Related source file is "D:/async_fifo/wptr_full.vhd".
Found 5-bit register for signal <wptr>.
Found 1-bit xor2 for signal <$n0005> created at line 46.
Found 1-bit xor2 for signal <$n0006> created at line 46.
Found 1-bit xor2 for signal <$n0007> created at line 46.
Found 1-bit xor2 for signal <$n0008> created at line 46.
Found 5-bit comparator equal for signal <$n0010> created at line 52.
Found 1-bit register for signal <w_full1>.
Found 5-bit register for signal <wbin>.
Found 5-bit adder for signal <wbinnext>.
Summary:
inferred 11 D-type flip-flop(s).

inferred 1 Adder/Subtractor(s).
inferred 1 Comparator(s).
Unit <wptr_full> synthesized.
Synthesizing Unit <dpram>.
Related source file is "D:/async_fifo/dpram.vhd".
Found 16x8-bit dual-port block RAM for signal <ram>.
----------------------------------------------------------------------| mode
| write-first
|
|
| aspect ratio
| 16-word x 8-bit
|
|
| clock
| connected to signal <wclk>
| rise |
| dual clock
| connected to signal <rclk>
| rise |
| dual enable
| connected to internal node
| high |
| write enable
| connected to internal node
| high |
| address
| connected to signal <waddr>
|
|
| dual address
| connected to signal <raddr>
|
|
| data in
| connected to signal <wdata>
|
|
| data out
| not connected
|
|
| dual data out | connected to signal <rdata>
|
|
| ram_style
| Auto
|
|
----------------------------------------------------------------------Summary:
inferred 1 RAM(s).
Unit <dpram> synthesized.
Synthesizing Unit <async>.
Related source file is "D:/async_fifo/async_fif0.vhd".
Unit <async> synthesized.
===============================================================
==========
*
Advanced HDL Synthesis
*
===============================================================
==========
Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...
===============================================================
==========
HDL Synthesis Report

Macro Statistics
# Block RAMs
:1
16x8-bit dual-port block RAM
:1
# Adders/Subtractors
:2
5-bit adder
:2
# Registers
: 10
1-bit register
:2
5-bit register
:8
# Comparators
:2
5-bit comparator equal
:2
# Xors
:8
1-bit xor2
:8
===============================================================
==========
===============================================================
==========
*
Low Level Synthesis
*
===============================================================
==========
Register <wbin_4> equivalent to <wptr_4> has been removed
Register <rbin_4> equivalent to <rptr_4> has been removed
Optimizing unit <async> ...
Optimizing unit <wptr_full> ...
Optimizing unit <rptr_empty> ...
Loading device for application Rf_Device from file 'v50.nph' in environment D:/Xilinx.
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block async, actual ratio is 3.
===============================================================
==========
*
Final Report
*
===============================================================
==========
Final Results
RTL Top Level Output File Name : async.ngr
Top Level Output File Name
: async
Output Format
: NGC
Optimization Goal
: Speed

Keep Hierarchy
Design Statistics
# IOs

: NO
: 24

Macro Statistics :
# RAM
:1
#
16x8-bit dual-port block RAM: 1
# Registers
: 10
#
1-bit register
:2
#
5-bit register
:8
# Adders/Subtractors
:2
#
5-bit adder
:2
# Comparators
:2
#
5-bit comparator equal
:2
Cell Usage :
# BELS
: 48
#
GND
:1
#
LUT1_L
:8
#
LUT2
:4
#
LUT2_D
:2
#
LUT2_L
:4
#
LUT3_D
:2
#
LUT4
:2
#
LUT4_L
:8
#
MUXCY
:8
#
VCC
:1
#
XORCY
:8
# FlipFlops/Latches
: 40
#
FDR
: 39
#
FDS
:1
# RAMS
:1
#
RAMB4_S16_S16
:1
# Clock Buffers
:2
#
BUFGP
:2
# IO Buffers
: 22
#
IBUF
: 12
#
OBUF
: 10
===============================================================
==========
Device utilization summary:
--------------------------Selected Device : 2s50pq208-5

Number of Slices:
Number of Slice Flip Flops:
Number of 4 input LUTs:
Number of bonded IOBs:
Number of BRAMs:
Number of GCLKs:

31 out of 768 4%
40 out of 1536 2%
30 out of 1536 1%
24 out of 144 16%
1 out of
8 12%
2 out of
4 50%

===============================================================
==========
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE
REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal
| Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
rclk
| BUFGP
| 21 |
wclk
| BUFGP
| 21 |
-----------------------------------+------------------------+-------+
Timing Summary:
--------------Speed Grade: -5
Minimum period: 10.671ns (Maximum Frequency: 93.712MHz)
Minimum input arrival time before clock: 10.163ns
Maximum output required time after clock: 10.481ns
Maximum combinational path delay: No path found
Timing Detail:
-------------All values displayed in nanoseconds (ns)
===============================================================
==========
Timing constraint: Default period analysis for Clock 'rclk'
Clock period: 10.671ns (frequency: 93.712MHz)
Total number of paths / destination ports: 119 / 20
-------------------------------------------------------------------------

Delay:
10.671ns (Levels of Logic = 6)
Source:
F3/r_empty1 (FF)
Destination:
F3/r_empty1 (FF)
Source Clock: rclk rising
Destination Clock: rclk rising
Data Path: F3/r_empty1 to F3/r_empty1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------FDS:C->Q
5 1.292 1.740 F3/r_empty1 (F3/r_empty1)
LUT3_D:I2->LO
1 0.653 0.000 F3/rptr_empty_rbinnext<0>lut (N155)
MUXCY:S->O
1 0.784 0.000 F3/rptr_empty_rbinnext<0>cy
(F3/rptr_empty_rbinnext<0>_cyo)
XORCY:CI->O
5 0.500 1.740 F3/rptr_empty_rbinnext<1>_xor
(F3/rbinnext<1>)
LUT2:I0->O
1 0.653 1.150 F3/r_empty378_SW0_SW0 (N150)
LUT4_L:I1->LO
1 0.653 0.100 F3/r_empty378_SW0 (N142)
LUT4_L:I3->LO
1 0.653 0.000 F3/r_empty378 (F3/r_empty)
FDS:D
0.753
F3/r_empty1
---------------------------------------Total
10.671ns (5.941ns logic, 4.730ns route)
(55.7% logic, 44.3% route)
===============================================================
==========
Timing constraint: Default period analysis for Clock 'wclk'
Clock period: 10.671ns (frequency: 93.712MHz)
Total number of paths / destination ports: 119 / 20
------------------------------------------------------------------------Delay:
10.671ns (Levels of Logic = 6)
Source:
F2/w_full1 (FF)
Destination:
F2/w_full1 (FF)
Source Clock: wclk rising
Destination Clock: wclk rising
Data Path: F2/w_full1 to F2/w_full1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------FDR:C->Q
5 1.292 1.740 F2/w_full1 (F2/w_full1)
LUT3_D:I2->LO
1 0.653 0.000 F2/wptr_full_wbinnext<0>lut (N154)
MUXCY:S->O
1 0.784 0.000 F2/wptr_full_wbinnext<0>cy
(F2/wptr_full_wbinnext<0>_cyo)
XORCY:CI->O
5 0.500 1.740 F2/wptr_full_wbinnext<1>_xor
(F2/wbinnext<1>)

LUT2:I0->O
1 0.653 1.150 F2/w_full385_SW0_SW0 (N148)
LUT4_L:I3->LO
1 0.653 0.100 F2/w_full385_SW0 (N140)
LUT4_L:I3->LO
1 0.653 0.000 F2/w_full385 (F2/w_full)
FDR:D
0.753
F2/w_full1
---------------------------------------Total
10.671ns (5.941ns logic, 4.730ns route)
(55.7% logic, 44.3% route)
===============================================================
==========
Timing constraint: Default OFFSET IN BEFORE for Clock 'rclk'
Total number of paths / destination ports: 42 / 31
------------------------------------------------------------------------Offset:
10.163ns (Levels of Logic = 7)
Source:
rinc (PAD)
Destination:
F3/r_empty1 (FF)
Destination Clock: rclk rising
Data Path: rinc to F3/r_empty1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
4 0.924 1.600 rinc_IBUF (rinc_IBUF)
LUT3_D:I1->LO
1 0.653 0.000 F3/rptr_empty_rbinnext<0>lut (N155)
MUXCY:S->O
1 0.784 0.000 F3/rptr_empty_rbinnext<0>cy
(F3/rptr_empty_rbinnext<0>_cyo)
XORCY:CI->O
5 0.500 1.740 F3/rptr_empty_rbinnext<1>_xor
(F3/rbinnext<1>)
LUT2:I0->O
1 0.653 1.150 F3/r_empty378_SW0_SW0 (N150)
LUT4_L:I1->LO
1 0.653 0.100 F3/r_empty378_SW0 (N142)
LUT4_L:I3->LO
1 0.653 0.000 F3/r_empty378 (F3/r_empty)
FDS:D
0.753
F3/r_empty1
---------------------------------------Total
10.163ns (5.573ns logic, 4.590ns route)
(54.8% logic, 45.2% route)
===============================================================
==========
Timing constraint: Default OFFSET IN BEFORE for Clock 'wclk'
Total number of paths / destination ports: 50 / 39
------------------------------------------------------------------------Offset:
10.163ns (Levels of Logic = 7)
Source:
winc (PAD)
Destination:
F2/w_full1 (FF)
Destination Clock: wclk rising

Data Path: winc to F2/w_full1

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------IBUF:I->O
4 0.924 1.600 winc_IBUF (winc_IBUF)
LUT3_D:I1->LO
1 0.653 0.000 F2/wptr_full_wbinnext<0>lut (N154)
MUXCY:S->O
1 0.784 0.000 F2/wptr_full_wbinnext<0>cy
(F2/wptr_full_wbinnext<0>_cyo)
XORCY:CI->O
5 0.500 1.740 F2/wptr_full_wbinnext<1>_xor
(F2/wbinnext<1>)
LUT2:I0->O
1 0.653 1.150 F2/w_full385_SW0_SW0 (N148)
LUT4_L:I3->LO
1 0.653 0.100 F2/w_full385_SW0 (N140)
LUT4_L:I3->LO
1 0.653 0.000 F2/w_full385 (F2/w_full)
FDR:D
0.753
F2/w_full1
---------------------------------------Total
10.163ns (5.573ns logic, 4.590ns route)
(54.8% logic, 45.2% route)
===============================================================
==========
Timing constraint: Default OFFSET OUT AFTER for Clock 'rclk'
Total number of paths / destination ports: 9 / 9
------------------------------------------------------------------------Offset:
10.481ns (Levels of Logic = 1)
Source:
F1/Mram_ram_inst_ramb_0 (RAM)
Destination:
rdata<7> (PAD)
Source Clock: rclk rising
Data Path: F1/Mram_ram_inst_ramb_0 to rdata<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------RAMB4_S16_S16:CLKB->DOB7 1 3.774 1.150 F1/Mram_ram_inst_ramb_0
(rdata_7_OBUF)
OBUF:I->O
5.557
rdata_7_OBUF (rdata<7>)
---------------------------------------Total
10.481ns (9.331ns logic, 1.150ns route)
(89.0% logic, 11.0% route)
===============================================================
==========
Timing constraint: Default OFFSET OUT AFTER for Clock 'wclk'
Total number of paths / destination ports: 1 / 1
------------------------------------------------------------------------Offset:
8.589ns (Levels of Logic = 1)
Source:
F2/w_full1 (FF)

Destination:
almost_wfull (PAD)
Source Clock: wclk rising
Data Path: F2/w_full1 to almost_wfull
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- -----------FDR:C->Q
5 1.292 1.740 F2/w_full1 (F2/w_full1)
OBUF:I->O
5.557
almost_wfull_OBUF (almost_wfull)
---------------------------------------Total
8.589ns (6.849ns logic, 1.740ns route)
(79.7% logic, 20.3% route)
===============================================================
==========
CPU : 9.89 / 10.25 s | Elapsed : 10.00 / 11.00 s
-->
Total memory usage is 84320 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)