Methods to Improve Device Scaling in CMOS Technologies

R. Gangadhar Reddy, Mtech student Vardhman College of engineering B.V.S.L.Bharathi, Associate Professor, Vardhman College of engineering

Abstract:
The phenomenon of short channel effects (SCEs) in metal-oxide-semiconductor field effect transistors (MOSFETs) has been there since many years. The scaling of conventional CMOS devices significantly beyond the 90-nm technology node will be challenging, due to limitations such as sub threshold leakage and gate-dielectric leakage. To overcome some of the problems associated with planar CMOS device scaling, advanced MOSFET structures such as the ultrathin-body SOI single-gate transistor and the double-gate transistor have been explored. These structures enable more aggressive device scaling because of their ability to control short channel effects more effectively. A more practical double-gate MOSFETs structure (DG MOSFETs also known as MuGFETs FinFETs,) was developed, with a process flow similar to that of conventional SOI CMOS processes. This additional gate would help strengthen the immunity of the channel from penetration effects of the drain electric field. Double gate are thus a better option from the point of view of long-term scalability and extendibility to future CMOS technologies. Keywords: Scaling, Multi gate, Fin Fet, SCE