Silicon

https://doi.org/10.1007/s12633-021-01095-3

ORIGINAL PAPER

Performance Analysis of Gate-Stack Dual-Material DG MOSFET Using

Work-Function Modulation Technique for Lower Technology Nodes
Satish K. Das 1 & Umakanta Nanda 2 & Sudhansu M. Biswal 3 & Chandan Kumar Pandey 2 & Lalat Indu Giri 4

Received: 10 February 2021 / Accepted: 26 March 2021

# Springer Nature B.V. 2021

Abstract
Short channel effects (SCEs) along with mobility degradation has a great impact on CMOS technology below 100 nm. These
effects can be overcome by using gate and channel engineering techniques which will improve mobility of the charge carriers,
thus eventually improving drain current and trans-conductance of the device. In this work, the speed of operation for DG
MOSFET is improved by reducing the channel length where dual-material gate-stack is deployed to avoid the drain-induced
barrier lowering (DIBL) and hot carrier effects. In the presented device, the metal closer to the source and drain has higher and
lower work function, respectively which causes a significant decrement in the peak electric field at the drain side and so the SCEs.
The carrier mobility is also increased due to enhanced electric field in the channel, near the source, caused by higher work
function gate material which, in turn, increases the MOSFET’s driving current. The screening effect reducing SCEs and an
increment in the acceleration of the charge carriers in the channel are mainly attributed due to higher and lower threshold voltage
found near the source and drain, respectively.

Keywords DGMOSFET . Work function . Gate Stack . Dual Metal

1 Introduction
In the last decade, advancement in wireless and microwave
communications along with acceleration of Moore’s law has
an aggressive thrust for scaling in the standard MOSFET
structures [1]. Better analog and digital application along with
higher cut-off frequency can be achieved if the gate length is
reduced [2]. However, below 50 nm new configuration [3, 4]
must be proposed to have the better performance along with
reduced short-channel effects (SCEs) than the orthodox
MOSFET structures. As the channel length decreases, many
effects change the device performance. On the whole the main
characteristics that occur in short-channel MOSFETs are
DIBL, Hot Carrier Effect, Impact Ionisation and Mobility
degradation. Therefore, an additional gate with same source
and drain combination along with existing channel is required
to be incorporated [5]. In short channel devices, the source
come closer to drain so the horizontal electric field starts af-
fecting, thus decreasing the barrier width of the channel. This
phenomenon is called as Drain Induced barrier lowering
(DIBL) [6, 7]. With the decrease of channel length the poten-
tial contour becomes gradually two dimensional from a one

* Umakanta Nanda 1
Department of Electronics and Communication Engineering, Silicon
uk_nanda@yahoo.co.in Institute of Technology, Bhubaneswar, Odisha, India

Satish K. Das 2
School of Electronics Engineering, VIT-AP University, Inavolu,
satish.das@silicon.co.in Beside AP Secretariat, Near Vijayawada, Andhra Pradesh, India
Sudhansu M. Biswal
sudhansu.mohan@silicon.ac.in 3
Department of Electronics and Instrumentation Engineering, Silicon
Institute of Technology, Bhubaneswar, Odisha, India
Chandan Kumar Pandey
chandankumarpandey@gmail.com
4
Department of Electronics and Communication Engineering, NIT,
Lalat Indu Giri Goa, Ponda, Goa, India
lalat_indu@yahoo.com

Fig. 1 3-D Structure of DG-MOSFET
dimensional contour. As a result, a lesser gate voltage is nec-
essary to achieve threshold in a short-channel device. Very
high electric field in the channel causes hot carrier effects [8]
and impact ionisation as well as mobility degradation ocurres.
Therefore, an additional gate with same source and drain com-
bination along with existing structure is designed to regulate
the channel called double gate MOSFETs (DGMOSFETs).
The vicinity of both the gates leads to stronger quantum-
mechanical confinement effects so that it will have better con-
trol of threshold voltage. This combination has the benefits of
increasing the overall current as this structure is analogous to
two transistors mounted back to back. Figure 1 represents the
3D structure of Double Gate MOSFET with two gates placed
in top and bottom along with source and drain. By adding an
additional gate on the back side of the structure, the overall
gate capacitance of the channel becomes twice and as a con-
sequence of this, the channel potential is better controlled by
the gate electrodes, thus reducing the off current in the device.
The gate contact can be either a metal contact or poly silicon
material. The channel region is usually made lightly doped or
un-doped body to avoid the dopant fluctuation effects which
mainly affects the variation in threshold voltage. Higher car-
rier mobility could be achieved by lightly doped channel re-
gion, consequently reducing the drain-to-body capacitance
and improving the circuit performance. The recent study
shows that the Double gate (DG) MOSFETs with much better
RF and analog performance can be a replacement for the con-
ventional MOSFET [9, 10]. However, in case of the circuit
implementation, these devices face with certain performance
related and dependability issues. Moreover, the symmetrical
structure can be converted to asymmetric so as to render better
performances. The asymmetric structure can be realized with
following modifications in symmetrical structures:
& By considering different types of gate materials for the top
and bottom gates i.e. difference in work function for both
the gates [11, 12].
& By applying different gate potentials for both the gates.
& Difference in top and bottom gate oxides.
& By considering the effect of self-alignment in top and
bottom gates
Silicon
These above modifications help to make the asymmetrical
DG devices (ADG) more superior in comparison to the sym-
metrical DG devices so that threshold voltage rolls off and
current switching ratio (Ion/Ioff) can be improved. Similarly,
tuning the functionality of the front gate through the biasing
of the bottom gate of DG MOSFET has a number of significant
effects for circuit applications, such as reduction in parasitic
effects and customized layout design area, offering supplemen-
tary circuit functionalities for better channel control and suscep-
tible to process variation and to achieve higher speed and con-
suming low power with respect to equivalent conventional cir-
cuits. Another alternative to enhance the performance without
further downscaling the device is to add an underlap length in
DG-MOSFET. In subthreshold region of the operation, the in-
trinsic capacitance of DG MOSFET is nearly independent of
the channel length and its value is found to be negligible.
Therefore, the parasitic capacitances are the dominant constitu-
ent of effective gate capacitance in DG-MOSFET operating in
the subthreshold region. The fringe capacitance in DG
MOSFET can be significantly reduced with an optimum value
of the underlap length, thus improving the performance and
reducing the power dissipation in subthreshold region.
However, adding underlap lengths causes a slight increase in
the channel resistance which results to a small reduction in ON
current. Next, a Graded-Channel Gate-Stack Double Gate
MOSFET (GCGS DG MOSFET) structure is found to be ca-
pable in dealing essentially with the hot-carrier effects [13]. It
not just overcomes some of the SCEs but also improves the
performances of the existing DG-MOSFETs. Graded channel
(GC) devices i.e. non-uniform doping concentrations across the
channel acts as an alternative solution for reducing the SCEs
and improving the device performance. The asymmetric chan-
nel or graded channel in DG MOSFETs shows benefits like
reduced parasitic bipolar effects exhibited by uniformly doped
devices, flexible threshold voltage roll-off, and disabling the
restriction of hot electron degradation effects found in uniform-
ly doped MOSFETs. The doping in the channel region of grad-
ed channel devices is formed by a tilted ion implantation meth-
od. In this device, the important feature is that the high doping
concentration near the source side can maintain the threshold
voltage, while low doping concentration ensures high mobility
in the channel, reducing the peak electric field, and the effect of
impact ionization near the drain end. Therefore, such structure
has the ability to reduce DIBL, improves (Ion/Ioff) ratio and
suppress the potential barrier alongside the channel for im-
proved carrier transport. Thus this device can play the major
role in limiting the SCEs and improving the analog and RF
performance. However, graded-doping for a small channel
length MOSFET is a great challenge to achieve with the
existing fabrication technology.
Furthermore, tunneling leakage current has become the pri-
mary limitation due to the over scaling of SiO2 layer up to
1.5 nm. This current will dominate the total current as it would
Silicon

& In addition to gate oxide thickness scaling, another tech-

nique to improve short-channel characteristics is
well/channel engineering. By changing the doping profile
in the channel region, the distribution of the electric field
and potential contours can be changed. The goal is to
optimize the channel profile to minimize the OFF-state
leakage while maximizing the linear and saturated drive
currents.
& Further, dual material gate stack with two different metal
Fig. 2 Cross sectional view of DGMOSFET with high-k and low-k gate
gates as shown in Fig. 3 are used to reduce the DIBL and
oxide stack hot carrier effects.
& The metal closer to the source is kept at higher work func-
tion and closer to the drain has lower work function [22].
be 10A in an IC having 1 mm2 dielectric area [14]. A high-k Hence the former is called as control gate and the latter is
dielectrics in the manufacturing process has its own bottleneck called as the screen gate.
as they react between themselves and the silicon substrate and & A step potential is created at the interface of the two metal
gate, [15] lowering the surface mobility greater than the Si/ gates due to the above arrangement consequently reducing
SiO2 system. These can be avoided by implanting a thin SiO2 the peak electric field at the drain end and the SCEs.
interfacial film in the middle of the silicon substrate and high- & The carrier mobility is increased because of enhanced field
k dielectric, which is called stack technology. Sometimes met- in the channel built by dual material gate.
al gate is also employed instead of a poly-Si. Deploying gate
oxide stack having high-K materials [16, 17] such as HfO2,
Al2O3 with interfacial SiO2 layer as shown in Fig. 2, consid-
erably limits leakage current through the gate and also avoids
2 Device Structure and Simulation Set-up
interfacial scattering in the interface of Si-SiO2.
Deploying dual material [23] or tri-material gate has its own
In order to improve DC and analog/RF parameters of DG
advantages. This is called as gate engineering [24]. Figure 4.a
MOSFET, in the proposed work:
demonstrates the cross sectional view of the single material
DGMOSFET simulated using Silvaco Atlas tool. Adhering to
& The channel length is decreased as much as possible to
the International Roadmap for Semiconductor Technology
enhance the speed of operation and device density in the
(ITRS) standards, several parameters are measured. Having
chip.
stacked oxide dielectric of SiO2 and HfO2 the structure is
& The multiple material gate structures reduces different
symmetric with double layered gate where pacers are
SCEs like DIBL, subthreshold swing, threshold voltage
amended with air for the simulation purpose.
roll-off, hot carrier effects, leakage current and enhances
The cross sectional view of the dual material DGMOSFET
electrostatic control, drain current, and carrier mobility in
is depicted in Fig. 4b. The gate length (Lg), source/drain
comparison to single material gate devices. Gate material
lengths, and channel thickness (tsi) of the proposed device
engineered structure has superior control towards the re-
are chosen to be 26 nm, 10 nm, and 16 nm respectively. The
duction of SCEs in Silicon on Insulator (SOI) transistors
doping concentration of the uniform n-type source and drain
[18]. These transistors are capable of decrease the parasitic
region is considered as 1020/cm3 whereas the channel region is
capacitances and SCEs compared to conventional transis-
doped with doping 1016/cm3. The construction of the device is
tors [19].
similar to the double layered gate and stacked oxide dielectric
& In the DMG-MOSFET, the work function of metal gate1
(M1) is greater than metal gate2 (M2) i.e., ФM1 > ФM2
and hence, threshold voltage which has the inherent ad-
vantage of improving the gate transport efficiency by
modifying the electric field pattern and the surface poten-
tial profile along the channel. A dual-material gate
MOSFET structure can provide improvent in the reduc-
tion of SCE since the step-shape in the surface potential
profile screens the effects of drain on the device channel,
also resulting in an increase the carrier transport efficiency
by increasing the average Electrid Field [20, 21].
Fig. 3 Cross sectional view of double gate dual material MOSFET

Fig. 4 a. Single material DG-MOSFET with channel length 26 nm. b. Dual metal DG-MOSFET with channel length 26 nm
of SiO2 and HfO2 where spacers are taken as air for the pur-
pose of simulation. Work function of metal 1 and metal 2 are
considered as 4.1 eV and 4.4 eV, respectively.
3 Results and Discussion
From simulation result the transfer characteristics obtained for
DM and SM DG-MOSFET has been compared. And the ef-
fect of gate material and work function variations on DG
MOSFET has been analysed.
3.1 Impact of Dual-Material on DG-MOSFETs
In this section, the impact of two gate material laterally con-
nected with different work function along with gate-stack on
performance of the DG MOSFET is investigated and analyzed
in details. Various significant DC and analog/RF performance
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parameters, such as drain current, transconductance, gate ca-
pacitance, cut-off frequency and maximum frequency are an-
alyzed for the proposed device.
Figure 5. a shows the Id vs Vgs for single and dual material
DGMOSFET. This result shows a clear distinction that for
dual material DG MOSFET the current is higher at a certain
Vgs as compared to single material DG MOSFET. This indi-
cates better switching characteristics for the proposed dual
material DG MOSFET for polysilicon and dual metal.
Figure 5 (b) depicts the variation of the trans-conductance
with respect to Gate Voltage (gm vs Vgs) for single and dual
material DGMOSFET. It can be seen that the dual material
DGMOSFET has higher trans-conductance value as com-
pared to single material DGMOSFET up to a certain gate
voltage. Transconductance is the measure of rate of change
in the drain current with respect to the change in gate-source
voltage. As the metal-semiconductor work-function differ-
ence (Φ MS ) increases for dual-material DG-MOSFET,
Silicon
Fig. 5 Variation of (a) Drain
current (b) Trans-conductance
with Gate-Source voltage
channel inversion happens at lower gate-source voltage and
eventually, transconductance in dual-material DG-MOSFET
is found to be more as compared to Single-material DG-
MOSFET for low range of gate voltage.
Figure 6 (a) demonstrates the variation of the gate to drain
capacitance as a function of Gate Voltage (Cgd vs Vgs) for
single and dual material DGMOSFET. It is observed that the
dual material DGMOSFET have higher gate to drain capaci-
tance value as compared to single material DGMOSFET for a
given gate voltage. Figure 6 (b) shows the variation of the gate
to source capacitance as a function Gate Voltage (Cgs vs Vgs)
for single material and dual material DGMOSFET. It is ob-
served that the dual material DG MOSFET have higher gate to
source capacitance value as compared to single material
DGMOSFET for a given gate voltage. Figure 6 (c) shows
the variation of the gate capacitance as a function Gate
Voltage (C g g vs V g s ) for single and dual material
DGMOSFET. It is observed that the dual material
DGMOSFET have higher gate capacitance value as compared
to single material DGMOSFET for a given gate voltage. By
neglecting the overlap capacitances and considering inner and
outer fringing capacitances at source and drain terminals, Cgs
and Cgd are mainly composed of parasitic and intrinsic capac-
itances [25]. In case of the dual-metal used in the proposed
device, inversion capacitances near both source and drain re-
gions increase due to the lower work function of gate metal
used for the device. An increment in the metal-semiconductor
work-function difference (ΦMS) causes the formation of
Fig. 6 (a) Variation of the gate to drain capacitance (b) gate to source capacitance, and (c) gate capacitance as a function Gate Voltage
inversion layer in the channel at comparatively lower gate-
source voltage.
Figure 7 (a) shows the variation of cut-off frequency with
respect to gate voltage for single and dual material DG
MOSFET. Initially in dual metal the cut-off frequency is more
up to a certain gate voltage but after that it decreases as com-
pared to poly silicon. This mainly happens because the Cgg is
inversely proportional to cut-off frequency (Ft). The variation
of maximum frequency (fmax) with Vgs is demonstrated in
Fig.7 (b). Here it can be observed that above a level of Vgs
the fmax is higher in case of proposed double gate structure.
Table 1 demonstrates some of the important RF parameters of
both single material and dual material DGMOSFET when
gate terminal is biased at 1 V.
3.2 Influence of Metal Gate Work Function on DG
MOSFETs
The effect of change of gate materials of the projected Gate
Stack DGMOSFET on various performance parameters are
demonstrated here. Various significant performance parame-
ters are analyzed for the proposed device, such as trans-
conductance with respect to gate voltage (gm vs Vgs), drain
current with respect to gate voltage (Id vs Vgs), and gate ca-
pacitance with respect to gate voltage (Cgg vs Vgs) parameters.
Short channel effects (SCEs) are dominating the performance
of nano scale devices as the threshold voltage is reducing day by
day. To reduce these effects, the poly-Si gate materials are
 Silicon

Table 1 RF parameters of both single material and dual material
DGMOSFET at Vgs = 1 V
Parameters at Dual-Material DG- Single-Material DG-
(Vgs =1 V) MOSFET MOSFET
gm(S) 3.05×10−3 2.95×10−3
Cgg(fF) 80 53
fT(GHz) 0.7 1.15
fm(GHz) 0.15 0.2
replaced with metal gate materials. The threshold voltage can be
changed by changing the work function of different metals
employed in the gate of the MOSFET. Consequently, the leak-
age current can be controlled by properly choosing the threshold
voltage without changing the supply voltage. It also reduces the
SCEs. This change (reduction) in work function can be achieved
by heavily implanting nitrogen. However, the original function-
ality of the device remains unchanged.
The proposed DG MOSFET (Fig. 4.b) is uniformly doped
whose dimensions are depicted in Table 2. This structure is
simulated in Silvaco tools to analyse the influence of work
function engineering on the device. To avoid more threshold
variation while controlling the degradation of carrier mobility,
the doping concentration is considered as light as 1016 cm−3.
Silicon film thickness and oxides (SiO2, HfO2) thickness are
16 nm, 2 nm, 2 nm respectively. The channel length is consid-
ered to be 26 nm. The proposed DG MOSFET having metals of
various work functions (4.8 4.1, 4.8 4.4, 4.8 4.6ev) is simulated.
3.3 Impact of Varying Work Function Screen Gate
As per the results obtained, keeping the work function of one
metal constant, it can be observed that the DG MOSFETs with
second metal having higher work function has low leakage
current and higher threshold voltage as compared to DG
MOSFETs having lower work function. Variation of capaci-
tances (Gate capacitance, Gate to source capacitance, Gate to
drain capacitance) with gate voltage are also plotted. Figure 8.
Table 2 Assumed dimension of the proposed DG MOSFET
Name Length (nm) Width (nm)
Channel (Si) 26 16
Metal1 26 1
Metal2 26 1
Oxide (SiO2) 26 1
Oxide (HfO2) 26 1
Source (Si+) 10 16
Drain (Si+) 10 16
(a) shows the graph of Cgd with respect to Gate voltage and we
can observe that the device with higher metal work function
(4.6 eV) has more Cgd initially with respect to the device with
lower metal work function (4.1 eV), but after a certain thresh-
old gate voltage the capacitance of the device having higher
metal work function has less gate to drain capacitance than the
device with lower metal work function.
Figure 8 (b) shows the graph of Gate Capacitance (Cg) vs
Gate voltage and we can observe that the device with higher
metal work function (4.6 eV) has less or almost equal Cg
initially with respect to the device with lower metal work
function (4.1 eV), but after a certain threshold gate voltage
the capacitance of device having higher metal work function
has more gate capacitance than the device with lower metal
work function. Figure 8 (c) shows the graph of Cgs vs Gate
voltage and we can observe that the device with higher metal
work function (4.6 eV) has less Cgs initially with respect to the
device with lower metal work function (4.1 eV), but after a
certain threshold gate voltage the capacitance of device having
higher metal work function has more gate capacitance than the
device with lower metal work function. Figure 9 (a) shows the
graph of variation of Drain current with respect to Gate volt-
age for different metal work function. The device with higher
metal work function has less drain current variation as com-
pared to the device with lower metal work function. Figure 9
(b) shows the graph of Gm vs Gate voltage. The device with
higher metal work function has less Gm initially with respect

Fig. 7 (a) Variation of cut off frequency with Gate-Source voltage for polysilicon and dual metal (b) Variation of max frequency of oscillation with Gate-
Source voltage for polysilicon and dual metal
Silicon

Fig. 8 Variation of (a) Gate to Drain capacitance (b) Gate capacitance (c) Gate-Source capacitance with Gate-Source voltage for dual metal with
changing metal work function

Fig. 9 Variation of (a) drain

current (b) Trans-conductance
with Gate-Source voltage for dual
metal with changing metal work
function

to the device with lower metal work function (4.1 eV). The gm g g
former is reduced than the later after certain threshold voltage. fT ¼ ffi≈  m
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ≈ m ð1Þ
C gd 2π C gd þ C gs 2πC gg
Figure 10 (a) shows the variation of cut-off frequency with 2πC gs 1 þ 2
respect to gate bias voltage. The result shows that if we in- C gs
crease the work function of other metal keeping one metal gm
work function constant in dual metal DG MOSFET, then the f max ≈ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
 ffi ð2Þ
  C gd
cut-off frequency decreases. Figure 10 (b) shows the variation 2πC gs 4 Rs þ Ri þ Rg gds þ gm
of maximum frequency of oscillation with respect to gate bias C gs
voltage. The result shows that if we increase the other metal
Where gm is the trans-conductance, Cgs is the gate to source
work function keeping one metal work function constant in
capacitance, Cgd is the gate to drain capacitance, Cgg is the
dual metal DG MOSFET, then the maximum frequency of
gate capacitance.
oscillation also decreases.
Figure 11 (a) shows that in dual metal DG MOSFET the
The approximate expression of important Radio Frequency
trans-conductance generation factor is higher when the work
figure of merits such as, fT, and fmax are given by

Fig. 10 Variation of (a) Cut-off

frequency (b) max frequency of
oscillation with Gate-Source
voltage for polysilicon and dual
metal

Fig. 11 Variation of (a) Trans-
conductance Generation Factor
(b) Gain bandwidth with Gate-
Source voltage for dual metal
with changing metal work
function
function difference of the two metal gates is lower and vice
versa. Figure 11 (b) shows that in dual metal DG MOSFET
initially the gain bandwidth is higher when the work function
difference of the two metal gates is higher but above certain
gate voltage the gain bandwidth is lower for the device where
the difference in work function between the metals is higher.
3.4 Linearity Analysis
Today it is required the modern communication system should
be less distortion and achieve better analog/RF performance.
Nonlinearity effect degrades the system performance. So it is
very necessary to control the non-linearity effect. For nonline-
arity performance various figure of merits(FOM) such as sec-
ond order voltage intercept point(VIP2), third order voltage
intercept point (VIP3) is studied. To suppress the non-linear
activities and better linearity performance given by gm2 and
gm3 (second order and third order derivative of gm1) the optimal
bias point is determined by gm3, at that point it suppress the
noise formed by gm3 [26]. From equation() and () we under-
stood that VIP2 is proportional to the ratio of gm1/ g2 and VIP3 is
proportional to the ratio of gm1 / gm3 respectively [27, 28].
gm
VIP2 ¼ 4 ð3Þ
g m2
Fig. 12 (a)Variation of VIP2 as a
function of Gate to source voltage
(b) Variation of VIP3 as a function
of Gate to source voltage for dual
metal with changing metal work
function
Silicon
rffiffiffiffiffiffiffiffiffiffiffiffi
g
VIP3 ¼ 24 m ð4Þ
g m3
∂I D
, gm ¼ ∂∂VI2D and gm ¼ ∂∂VI3:D
2 3
Where gm ¼ ∂V
gs gs gs
From fig. 12(a) and (b) it is concluded that there is a max-
imum peak at low VGS for M1 = 4.8 and M2 = 4.6, in compar-
ison to others. However, at M1 = 4.8 and M2 = 4.6 the plot is
more linear than others.
4 Conclusion
As SCEs and mobility degradation dictate the overall perfor-
mance of the MOSFETs, in this paper an approach has been
adopted to reduce the above dominance. The enhanced field in
the channel near the source built by dual-material gate helps
greatly to increase the mobility of the charge carriers, thus im-
proving the device’s driving current. Furthermore, the peak elec-
tric field at drain side is reduced because of the dual work function
provided by different metals at source and drain, the short channel
effects are also reduced. In fact, dual-material with different work
function introduces a sharp abrupt change in threshold voltage
along the channel which further leads to the screening effect at
drain, thus suppressing the SCEs. With dual-material
Silicon
configuration, the performance of MOSFETs has been improved
both in subthreshold and above threshold regime. Moreover, an
extensive analysis has been carried out to validate the proposed
work which shows that the dual material DGMOSFET has better
performance over polysilicon gate in almost every aspect.
Availability of Data and Material The authors confirm that the data
supporting the findings of this study are available within the article, its
supplementary materials or below mentioned references.
A ut ho r’ s Co nt r i b u t i o n s Satish K Das, Umakanta Nanda -
Conceptualization, methodology, simulation and investigation, Sudhansu M
Biswal, Chandan Kumar Pandey - Writing original draft preparation,
reviewing and editing, Lalat Indu Giri-Validation and overall correction.
Declarations
This article does not contain any studies with human participants or an-
imals performed by any of the authors.
Consent to Participate All authors freely agreed and gave their consent
to participate on this work.
Consent for Publication All authors freely agreed and gave their consent
for the publication of this paper.
Conflict of Interest The authors declare that they have no conflict of
interest.
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