Silicon

https://doi.org/10.1007/s12633-021-01195-0

ORIGINAL PAPER

A Physics Based Threshold Voltage Modeling of Trigate Junctionless

FinFETs Considering Gaussian Doping
S. Manikandan 1 & N. B. Balamurugan 2

Received: 26 February 2021 / Accepted: 8 June 2021

# Springer Nature B.V. 2021

Abstract
In this paper, the analytical modeling of Trigate Junctionless FinFETs has been explored. The analytical model expresses the
potential distribution, minimum center potential and threshold voltage. The variable separation method has been used to develop
the potential distribution and threshold voltage. Further, the analytical model analyzed for different device parameters of Fin
width, Fin height, Gate oxide thickness and gate work function. The analytical model results are compared with Synopsys TCAD
results which proves the validation of proposed analytical model.

Keywords FinFETs . Threshold voltage . Electrostatic potential . Trigate . Gaussian doping

1 Introduction drain current and RF performance of halo based Tunnel

The scaling of CMOS transistors leads to increased device
density and performance of the IC industry [1]. This aggres-
sive scaling not only improved the device performance also
degrades the device electrical characteristics by short channel
effects. These short channel effects are subthreshold swing,
leakage current and Drain Induced Barrier Lowering (DIBL)
[2]. To alleviate these second order effects certain device
structure and conduction mechanism has been introduced in
classical MOSFETs [3, 4]. The Multigate structure has better
gate controllability and reduced short channel effects. Among
the several gate structure Trigate and surrounding gate based
transistors improves the device electrical characteristics [5–7].
The change in device conduction mechanism via tunneling
and junctionless based transistors have been under research
for decade [8–11]. Tunnel FETs reduces leakage current and
have better subthreshold characteristics than the conventional
MOSFETs. The analytical modeling of threshold voltage,
* N. B. Balamurugan
nbbalamurugan@tce.edu
S. Manikandan
manikandans@scadengineering.ac.in
1
Department of ECE, SCAD College of Engineering and Technology,
Tirunelveli, India
2
Department of ECE, Thiagarajar College of Engineering,
Madurai, Tamilnadu, India
FETs were reported [12–14]. However, the tunneling conduc-
tion mechanism reduces the device drive current which direct-
ly affects the I ON /I OFF ratio. On the other hand, the
Junctionless based transistors sustain short channel effects
and improves the device drive current and transconductance
[15, 16]. The analytical modeling of double gate based
junctionless transistors has been proposed earlier [17].
FinFETs becomes successful candidate which alleviate the
short channel effects and improves the device performance.
However, the ultra-deep shallow source/drain junction in
FinFETs becomes very hard during fabrication process also
requires high-cost annealing techniques. In this aspect, a
Junctionless based transistor has homogenous doping concen-
tration across the device reduces fabrication cost and give
better immunity against the short channel effects. The
junctionless transistors has introduced in 2009 and demon-
strated in 2010 [3, 18, 19]. FinFETs based transistors severely
affected by reliability issues of self-heating effects, random
dopant fluctuations and other thermal related issues. Hence,
the introduction of junctionless concept in FinFETs gives bet-
ter immunity against short channel effects and can withstand
upcoming technology node. The analysis of different gate
structure and the corresponding performance study have been
reported [20].
Several analytical modeling of Junctionless transistors and
FinFETs have been presented [21–26]. Most of them uses
parabolic approximation techniques which assumes the chan-
nel potential. However, the ultra-thin FinFETs requires
 Silicon

accurate physics-based modeling of potential distribution and can be neglected the reason behind this is silicon is fully de-
threshold voltage. The variability of threshold voltage, ran- pleted under subthreshold condition. The two-dimensional
dom dopant fluctuations, work function and line edge rough- poisons equation is follows.
ness are studied presented junctionless transistors using
TCAD simulation [27]. In our previous work, we studied the ∂2 ψðx; yÞ ∂2 ψðx; yÞ −qN d ðyÞ
þ ¼ ; −tch =2 < x
different doping configuration of Gaussian, uniform and grad- ∂x2 ∂y2 εsi
ual doping concentration for Trigate Junctionless FinFETs. < tch =2; 0 < y < L ð1Þ
We compared the device electrical characteristics of drain cur- "   #
rent, transconductance and substrate methodology to reduce y−ypeak 2
Nd ðyÞ ¼ Npeak exp − pffiffiffiffiffiffiffi ð2Þ
the device substrate current [28]. RF simulation study of cut- 2∝n
off frequency, maximum frequency of oscillation, gate capac-
itance and stability/linearity analysis of uniform and Gaussian Where q is the electron charge, tch is the channel thickness,
doped Trigate Junctionless FinFETs has been presented ψ (x, y) is the potential distribution, NPeak is the peak doping
[29–31]. concentration, ypeak is position of peak doping concentration
In this paper, we developed physics based analytical at channel and ∝n is the straggle length. The solution of poi-
modeling of potential distribution minimum center potential sons equation can be obtained from variable separation meth-
and threshold voltage for Gaussian doped Trigate Junctionless od by dividing two-dimensional poisons equation into one
FinFETs from poisons equation with proper boundary condi- dimensional poison equation and 1D Laplace equation as fol-
tions using variable separation method. The developed model lows.
verified with Synopsys TCAD simulation results for valida-
tion of analytical model. The drift diffusion model, Band gap ψðx; yÞ ¼ ψ1 ðyÞ þ ψ2 ðx; yÞ ð3Þ
narrowing, SRH and Auger recombination and Philips unified
The solution of potential distribution can be obtained from
mobility model for the consideration of mobility effects are
the following differential equations.
considered for TCAD simulation. The quantization effects are
not considered which neglectable for the channel length above ∂2 ψ1 ðyÞ −qN d ðyÞ
7 nm. ¼ ð4Þ
∂y2 εsi
∂2 ψ2 ðx; yÞ ∂2 ψ2 ðx; yÞ
þ ¼0 ð5Þ
∂x2 ∂y2
2 Analytical Model
The boundary conditions to obtain potential distribution of
Fig. 1 shows the schematic view of Trigate Gaussian doped Trigate Gaussian doped Junctionless FinFETs are shown be-
Junctionless FinFETs with channel length of 20 nm, Fin thick- low.
ness of 10 nm, Fin height of 42 nm, gate work function of 
4.2 eV, gate oxide thickness of 0.6 nm and Gaussian doping −εsi ∂ψðx; yÞ 
ψG −ψðx; yÞ ¼ t ox : : ð6Þ
with peak doping concentration of Npeak = 1 × 1019 cm−3. The εox ∂y y¼0
Gaussian doping has been implemented with the following 
εsi ∂ψðx; yÞ 
equation is shown in Table 1. ψG −ψðx; yÞ ¼ t ox : : ð7Þ
εox ∂y y¼tch
2.1 Electrostatic Potential ψð0; yÞ ¼ ψs ðxÞ ¼ V bi ð8Þ
ψðL; yÞ ¼ ψd ðxÞ ¼ V bi þ V ds ð9Þ
The potential distribution across the silicon Fin can be obtain-  
ed from the poison’s equation. The minority charge carriers 1  
ψG ¼ V gs − ΦM −χ−E geff ð10Þ
q

Table 1 Device parameters Where εsi, εoxis the dielectric constant of Silicon and SiO2
respectively, Vgs is gate to source voltage, Vds is drain to
Parameter Value
source voltage, ΦM is the gate work function, χ is silicon
Channel Length (Lg) 20 nm affinity, Vbi is built in potential. The solution of 1D poisons
Fin width (tsi) 10 nm equations using the boundary conditions from (6) to (7) can be
Fin Height (H) 42 nm obtained as,
Gate work function 4.2 eV
−qN d ðyÞ 2
Peak Doping Concentration (Npeak) 1×1019 cm−3 ψ 1 ð yÞ ¼ y þ An y þ Bn ð11Þ
2εsi
Silicon

Fig. 1 Cross sectional view

Gaussian doped Trigate
Junctionless FinFETs

qN d ðyÞt ch
An ¼ ð12Þ The coefficients Cn, Dn can be derived using the boundary
2εsi conditions (6) to (9) and λ denotes the natural length.
εsi

Bn ¼ ψG þ :t eff :An ð13Þ 2L qN d ðyÞL2
εox Cn ¼   ψ1 ðyÞð−1Þn þ ð ð −1 Þ n
−1 Þ
ηH eff η2 λ
The solution of ψ2(x, y) using the boundary conditions η2 cosh
L
from (7) to (8) can be expressed as follows,
ð15Þ
 ηy
    ηx 
∞ η H eff −x
ψ2 ðx; yÞ ¼ ∑ sin C n sinh þ Dn sinh
n¼1 L λ λ
ð14Þ

     
2 V gs −V fb −C 2 qN d ðyÞ 2 qN d ðyÞL2 ðð−1Þn −1Þ
Dn ¼   η − V gs −V fb − L −C 1 L−C 2 þ ð16Þ
ηH eff λ 2εsi η2 λ
ηcosh
L

pffiffiffiffiffiffiffiffiffiffiffiffiffiffi εox
Where, η ¼ nπ =L ; n ¼ 1, λ ¼ t ch ð4t ox εsi þ 8t ch 8εox: Þ
The total electrostatic potential can be written as

 ηy
    ηx 
−qN d ðyÞ 2 ∞ η H eff −x
ψðx; yÞ ¼ y þ An y þ Bn þ ∑ sin C n sinh þ Dn sinh ð17Þ
2εsi n¼1 L λ λ

center potential and threshold voltage can be obtained from

the following expressions.
2.2 Minimum Center Potential and Threshold Voltage
 t t  t ch
ch ch
The threshold voltage of Trigate Gaussian doped Junctionless ψmin x; ¼ ψ1 þ ψ2 xmin ; ð18Þ
2 2 2
FinFETs is defined as gate voltage is required to create min- 
imum center potential at center of Fin. Mostly minimum cen- ∂ψðx; yÞ 
¼0 ð19Þ
ter potential will appear on center of Fin which is located at tch/ ∂x x¼xmin
2 in subthreshold regime and top of the Fin at inversion re- 0 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1
1 @ C 1 −C 2 expðηLÞ
gime. Hence, the expression of minimum center potential will xmin ¼ þ ln   A ð20Þ
be helpful for deriving threshold voltage and drain current of η expðηLÞ C exp −ηL þ C
1 2
Trigate Gaussian doped Junctionless FinFETs. The minimum
 Silicon
 t ch
ψmin xmin ; ¼ Vf ð21Þ
2

 
qN d t 2ch εsi t eff 1  
V th ¼ þ :An − ΦM −χ−E geff
8εsi εox q
 
ηt ch
2λ
   ηx 
cos =
ηðL−xmin Þ
þ   C n sinh
sinh ηL λ λ
λ
3 Results and Discussion
Figure 2 shows the plot of doping concentration across the
silicon thickness for Gaussian doping (σ = 2, 4 nm) and uni-
form doping. The uniform doping concentration has a con-
stant doping concentration value of 1 × 1019 cm−3. In the
Gaussian doping, the peak doping concentration is fixed at
centre of the channel and reduced by straggle length (σ = 2,
4 nm) parameter. The broadening of the doping distributions
is controlled by the straggle length (σ) shown in the Eq. 2.
Figure 3 shows the plot of electrostatic potential compari-
son for uniform and Gaussian doped Trigate Junctionless
FinFETs at Vgs = Vds = 0. The potential barrier at the channel
is high in Gaussian doped structure compare to uniform dop-
ing. The reason behind this is due to the presence of variable
doping across the channel. The high potential barrier at the
fermi level ensures the reduced leakage current in the channel.
Thus, the Gaussian doped Trigate Junctionless FinFETs
shows better device performance than the uniform doping.
The close proximity between the model and simulation results
shows the accuracy of the results.
Fig. 2 Comparison of doping configuration for Trigate Junctionless
FinFETs
þ Dn sinh
min
ð22Þ
The plot of electrostatic potential of GDTG-JLFinFETs
along the channel for various gate voltage is shown in
Fig. 4. It is observed that, the increase in gate voltage from
0 V the electrostatic potential is increased due to the accumu-
lation of electrons at the channel. The increase in gate voltage
influences the electron mobility and enables the electrons
from source to drain. This result guarantees the GDTG-
JLFinFETs has better gate controllability and eliminates
Short Channel Effects (SCEs). The developed model matches
well with simulation results.
Figure 5 depicts the variation of electrostatic potential for
variation of drain to source voltage from 0 to 0.4 V. The
increase in drain to source voltage reflects the drain voltage
doesn’t affect the source which is responsible for Drain
Induced Barrier Lowering (DIBL). The potential barrier is
not affected by variation of drain voltage that shows Trigate
Gaussian doped Junctionless FinFETs can sustain short chan-
nel effects for forthcoming technology node. The results of
simulation data and model shows the accuracy of the proposed
model.
Figure 6 shows the plot of electrostatic potential variation
for different Fin width of 10, 12, 14 nm. It is evident from the
results that, the increase in Fin width from 10 nm to 12 nm and
Fig. 3 Comparison of electrostatic potential for Uniform and Gaussian
doping concentration of Trigate Junctionless FinFETs
Silicon
Fig. 4 Plot of electrostatic potential for variation of gate to source voltage
of Trigate Gaussian doped Junctionless FinFETs
14 nm the electrostatic potential as well as minimum center
potential is increased. Because of the increase in silicon thick-
ness the area of electron accumulation also increases which
leads to change in electrostatic potential. It is also noted that,
the GDTG-JLFinFETs can control device for increasing the
fin width that shows the better gate control over the channel.
Figure 7 shows the variation of electrostatic potential with
various peak doping concentration in Eq. 2. The higher dop-
ing concentration creates lower threshold voltage due to the
greater number of electrons in the channel as observed. The
increase in peak doping concentration increases the minimum
centre potential as well as the electrostatic potential at the
source/drain side. This shows the doping concentration in-
creases the electron mobility in the entire channel. The better
gate controllability is ensured in the GDTG-JLFinFETs.
Fig. 5 Plot of electrostatic potential for variation of drain to source
voltage of Trigate Gaussian doped Junctionless FinFETs
Fig. 6 Electrostatic potential variations of Fin width (FW) for Gaussian
Doped Trigate Junctionless FinFETs with FW = 10, 12, 14 nm
The plot of threshold voltage for various fin width is shown
in Fig. 8. It is evident from the figure that the increase in fin
thickness of GDTG-JLFinFETs decreases the threshold volt-
age. The reason behind this is due to the increased area of
silicon thickness. The increase in silicon or fin thickness also
rises the electron mobility in the channel there by decreasing
threshold voltage. However, the thicker Fin thickness leads to
threshold voltage roll off for GDTG-JLFinFETs. The simula-
tion results matched well with analytical model results.
The plot of threshold voltage variations along the channel
length for different Fin height of 30, 40, 50 nm is shown in
Fig. 9. The increase in Fin height decreases the threshold
voltage of GDTG-JLFinFETs. The threshold voltage is de-
creased by 0.01 V for increase in Fin height of every 10 nm.
This is because, with increase in fin height gate controllability
over the charge carriers in the channel lowers the threshold
Fig. 7 Plot of electrostatic potential variation for various peak doping
concentration

Fig. 8 Plot of threshold voltage variation for different Fin height FH = 30,
40, 50 nm
voltage of GDTG-JLFinFETs. In addition, the threshold volt-
age of GDTG-JLFinFETs is obtained from ~0.336 to 0.36 V
for a channel length of 10 nm. This shows better short channel
characteristics of GDTG-JLFinFETs.
The impact of peak doping concentration of GDTG-
JLFinFETs along the channel length is shown in Fig. 10.
The doping fluctuations is a serious problem in semiconductor
fabrication. Thus, the analysis of different doping concentra-
tion is necessary for GDTG-JLFinFETs. The channel length
above the 25 nm variation of threshold voltage for different
peak doping concentration is very less than the channel length
below 20 nm. This due to the inevitable short channel effects
for lower channel length. The results of simulation data match
well with the analytical model results.
Figure 11 shows the variation of threshold voltage for dif-
ferent gate work function along the channel length. The lower
gate work function (ΦM = 4.5 eV) exhibits lower threshold
voltage due to lower gate electric field over the charge carriers
Fig. 9 Plot of Threshold voltage along channel length for different fin
width of 10, 12, 14 nm
Silicon
Fig. 10 Variation of threshold voltage for different peak doping
concentration for Trigate Gaussian Doped Junctionless FinFETs
in the channel. It is also observed that higher gate work func-
tion shows better threshold voltage roll off in short channel
device. It is found that data obtained from the analytical model
are matched with the TCAD simulation results.
4 Conclusion
The analytical model of Gaussian Doped Trigate Junctionless
FinFETs has been investigated. The analytical expression of
electrostatic potential and threshold voltage has been obtained
from poisons equation using variable separation method. The
developed model further analyzed for variation of gate to
source voltage (Vgs), gate to drain voltage (Vds), fin width,
fin height, peak doping concentration and gate work function
for the model scalability. The Gaussian doping in the channel
enhances the Trigate Junctionless FinFETs electrostatic
Fig. 11 Variation of threshold voltage for different gate work function of
Trigate Gaussian doped Junctionless FinFETs
Silicon
potential and immunity against the threshold voltage roll off.
The analytical model results are validated against the TCAD
simulation results.
Acknowledgments The authors would like to thank Thiagarajar College
of Engineering, Madurai for providing continuous support for this work
Code Availability Not Applicable.
Author Contributions Writing - literature search and analysis, original
draft preparation: [Dr.S.Manikandan], Idea of the article, Resources,
Supervision: [Dr.N.B.Balamurugan].
Declarations
Ethics Approval and Consent to Participate All authors freely agreed
and gave their consent for the publication of this paper.
Consent for Publication All authors freely agreed and gave their consent
for the publication of this paper.
Conflicts of Iiterest/Competing Interests The authors have no relevant
financial or nonfinancial interests to disclose.
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