Logisim-constructed counters 1.

Asynchronous 3-bit up counter: Note you can use T-FFs instead of JK and fixing both inputs to 1; also, UP/DOWN counting can be changed using the trigger of the FFs (rising edge: DOWN count, falling edge: UP count)

2. Synchronous 4-bit up counter: Note: FFs are falling-edge triggered.

3. MOD-5 Asynchronous UP counter: FFs are falling-edge: asynchronous RESET was used.

4. Asynchronous counters using the inverted output (i.e. using rising edge for up counting and falling edge for down counting)

5. Ring counter: Set FF enable to 1 in order to enable clock recognition. Hold pushbutton to set initial 1 value at the first flip-flop. You may opt not to include FF enable in wiring. PGT.

6. Johnson counter: again set FF enable to 1 before using simulation. You can opt not to include it when you construct the circuit. PGT.

7. Synchronous UP/DOWN counter. Note U/D convention; only one function can be active at any time. This can also be derived using sequential circuit design. (FFs falling edge)

8. Presettable counters. Inverters at the asynchronous inputs were used to emulate their active-lowness; preset controls are located above; and are fed asynchronously (jammed) to the FFs when the lower-left input Active low parallel load enable is active. If both are inactive, counter counts UP.