MEWAR UNIVERSITY

Year of the Examination: Programme: M.Tech. 2nd Year 3rd Semester (CSE) Semester: 3rd Course Code: CSE-617 Total No. of Questions: No. of Questions to be attempted: All Course Title: High Performance Computer Architecture Maximum Marks: Total No. of Pages used: Time Allowed:

The candidates, before starting to write the solutions, should please check the Question Paper for any discrepancy, and also ensure that they have been delivered the question paper of right course no. and title.

------------------------------------------------------------------------------------------------------------------------------ASSIGNMENT-2 Q.1 Q.2 Q.3 Q.4 Q.5 Q.6 Q.7 Q.8 Describe the Von-Neumann architecture of computer? What is the difference between super scalar and super pipelined approach? Describe the techniques to design the computer with respect to improving performance? Explain the difference between multiprocessor and multicomputer. Explain the multiprocessor architecture in details with suitable example. What do you mean by parallel computers? Discuss the Flynns classification of computer architecture. What do mean by array and vector processors? Explain VLIW processor architecture. Write short notes on: a) Cluster computers b) Data flow computers c) Interconnection network Q.9 Q.10 Q.11 Q.12 Explain Distributed shared memory architecture. Explain the different ways to achieve parallelism in single processor system. Explain the evolution of computer architecture. Write short notes on: a) Reduction computer architecture b) Systolic architectures

Q.13

An operating system uses a Least Recently Used (LRU) page replacement algorithm. Consider the following page reference ordering (pages are referenced from left to right): 1, 8, 1, 7, 8, 2, 7, 2, 1, 8, 3 Determine the number of page faults that are generated for this particular LRU case assuming that the process has been allocated four page frames, and that initially, none of the pages are in the main memory?

Q.14 Q.15

What do you mean by virtual memory organization? Discuss different memory replacement policies. A set associative cache consists of 64 slots divided into 4-slot sets. Main memory contains 4K Blocks of 128 bytes each. Show the format of the main memory address.

------------------------------------------------------------End-------------------------------------------------------------Name: Roll No. Last Date of Submission: 25/03/2012