3/27/12

Gmail - (no subject)

ashutosh pradhan <ashu1.220791@gmail.com>

(no subject)
1 me

age

vidh a lakshmi < l.1990@gmail.com>

To: p a eek po al <pa ickpo al@gmail.com>, a h 1.220791@gmail.com

T e, Ma 27, 2012 a 3:48 PM

----------------------------------------------------------------------------------- Compan :
-- Enginee :
--- C ea e Da e: 14:58:49 03/27/2012
-- De ign Name:
-- Mod le Name: clahead - Beha io al
-- P ojec Name:
-- Ta ge De ice :
-- Tool e ion :
-- De c ip ion:
--- Dependencie :
--- Re i ion:
-- Re i ion 0.01 - File C ea ed
-- Addi ional Commen :
----------------------------------------------------------------------------------lib a IEEE;
e IEEE.STD_LOGIC_1164.ALL;
e IEEE.STD_LOGIC_ARITH.ALL;
e IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncommen he follo ing lib a decla a ion if in an ia ing
---- an Xilin p imi i e in hi code.
--lib a UNISIM;
-- e UNISIM.VComponen .all;
en i clahead i
Po ( A : in STD_LOGIC_VECTOR (3 do n o 0);
B : in STD_LOGIC_VECTOR (03 do n o 0);
S : o STD_LOGIC_VECTOR (4 do n o 0));
end clahead;
a chi ec e Beha io al of clahead i
ignal C: d_logic_ ec o (3 do n o 0);
begin
C(0)<=A(0) and B(0);
C(1)<= ((A(0) and B(0)) and (A(1) o B(1))) o (A(1) and B(1));
C(2)<= ((((A(0) and B(0)) and (A(1) o B(1))) o (A(1) and B(1))) and
(A(2) o B(2)))o (A(2) and B(2));
C(3)<= ((((((A(0) and B(0)) and (A(1) o B(1))) o (A(1) and B(1)))
and (A(2) o B(2)))o (A(2) and B(2))) and (A(3) o B(3)))o (A(3) and
B(3));
---WAIT FOR 50 NS;

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S(0)<=A(0) XOR B(0);

S(1)<=(A(1) XOR B(1)) XOR C(0);
S(2)<=(A(2) XOR B(2)) XOR C(1);
S(3)<=(A(3) XOR B(3)) XOR C(2);
S(4)<=C(3);
end Beha io al;

--------------------------------------------------------------------------------- Compan :
-- Enginee :
--- C ea e Da e: 15:23:54 03/27/2012
-- De ign Name: clahead
-- Mod le Name: /cad/ ilin /ha i h/ca _look_ahead_adde /CLAHEAD_TB. hd
-- P ojec Name: ca _look_ahead_adde
-- Ta ge De ice:
-- Tool e ion :
-- De c ip ion:
--- VHDL Te Bench C ea ed b ISE fo mod le: clahead
--- Dependencie :
--- Re i ion:
-- Re i ion 0.01 - File C ea ed
-- Addi ional Commen :
--- No e :
-- Thi e bench ha been a oma icall gene a ed ing pe
d_logic and
-- d_logic_ ec o fo he po of he ni nde e . Xilin ecommend
-- ha he e pe al a be ed fo he op-le el I/O of a de ign in o de
-- o g a an ee ha he e bench ill bind co ec l o he
po -implemen a ion
-- im la ion model.
-------------------------------------------------------------------------------LIBRARY ieee;
USE ieee. d_logic_1164.ALL;
USE ieee. d_logic_ n igned.all;
USE ieee.n me ic_ d.ALL;
ENTITY CLAHEAD_TB_ hd IS
END CLAHEAD_TB_ hd;
ARCHITECTURE beha io OF CLAHEAD_TB_ hd IS
-- Componen Decla a ion fo he Uni Unde Te
COMPONENT clahead
PORT(
A : IN d_logic_ ec o (3 do n o 0);
B : IN d_logic_ ec o (3 do n o 0);
S : OUT d_logic_ ec o (4 do n o 0)
);
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END COMPONENT;
--Inp
SIGNAL A :
SIGNAL B :

d_logic_ ec o (3 do n o 0) := (o he =>'0');
d_logic_ ec o (3 do n o 0) := (o he =>'0');

--O p
SIGNAL S :

d_logic_ ec o (4 do n o 0);

BEGIN
-- In an ia e he Uni Unde Te
: clahead PORT MAP(
A => A,
B => B,
S => S
);

(UUT)

b : PROCESS
BEGIN
-- Wai 100 n fo global e e o fini h
ai fo 100 n ;
-- Place

im l

A<="0001";
B<="0100";
ai fo 200 n ;
if(S="00101")
hen
a e
e epo
end if;
ai fo 20 n ;
A<="0101";
B<="1011";
ai fo 200 n ;
if(S="10000")
hen
a e
e epo
end if;
ai fo 20 n ;
A<="0100";
B<="0111";
ai fo 200 n ;
if(S="01011")
hen
a e
e epo
end if;
ai fo 20 n ;
A<="0010";
B<="0011";
ai fo 200 n ;
if(S="00101")
hen
a e
e epo
end if;

he e

"E o 1" e e i

e o;

"E o 2" e e i

e o;

"E o 3" e e i

e o;

"E o 4" e e i

e o;

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ai ; -- ill ai fo e e
END PROCESS;
END;

----------------------------------------------------------------------------------- Compan :
-- Enginee :
--- C ea e Da e: 15:27:55 03/27/2012
-- De ign Name:
-- Mod le Name: CLA_BCD2XS3 - Beha io al
-- P ojec Name:
-- Ta ge De ice :
-- Tool e ion :
-- De c ip ion:
--- Dependencie :
--- Re i ion:
-- Re i ion 0.01 - File C ea ed
-- Addi ional Commen :
----------------------------------------------------------------------------------lib a IEEE;
e IEEE.STD_LOGIC_1164.ALL;
e IEEE.STD_LOGIC_ARITH.ALL;
e IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncommen he follo ing lib a decla a ion if in an ia ing
---- an Xilin p imi i e in hi code.
--lib a UNISIM;
-- e UNISIM.VComponen .all;
en i CLA_BCD2XS3 i
Po ( X : in STD_LOGIC_VECTOR (03 do n o 0);
Y : o STD_LOGIC_VECTOR (4 do n o 0));
end CLA_BCD2XS3;
a chi ec e Beha io al of CLA_BCD2XS3 i
componen clahead i
Po ( A : in STD_LOGIC_VECTOR (3 do n o 0);
B : in STD_LOGIC_VECTOR (3 do n o 0);
S : o STD_LOGIC_VECTOR (4 do n o 0));
end componen clahead;
begin
con e e :clahead po map (X,"0011",Y);

end Beha io al;

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--------------------------------------------------------------------------------- Compan :
-- Enginee :
--- C ea e Da e: 15:32:43 03/27/2012
-- De ign Name: CLA_BCD2XS3
-- Mod le Name: /cad/ ilin /ha i h/ca _look_ahead_adde /cla_bcd2 3_ b. hd
-- P ojec Name: ca _look_ahead_adde
-- Ta ge De ice:
-- Tool e ion :
-- De c ip ion:
--- VHDL Te Bench C ea ed b ISE fo mod le: CLA_BCD2XS3
--- Dependencie :
--- Re i ion:
-- Re i ion 0.01 - File C ea ed
-- Addi ional Commen :
--- No e :
-- Thi e bench ha been a oma icall gene a ed ing pe
d_logic and
-- d_logic_ ec o fo he po of he ni nde e . Xilin ecommend
-- ha he e pe al a be ed fo he op-le el I/O of a de ign in o de
-- o g a an ee ha he e bench ill bind co ec l o he
po -implemen a ion
-- im la ion model.
-------------------------------------------------------------------------------LIBRARY ieee;
USE ieee. d_logic_1164.ALL;
USE ieee. d_logic_ n igned.all;
USE ieee.n me ic_ d.ALL;
ENTITY cla_bcd2 3_ b_ hd IS
END cla_bcd2 3_ b_ hd;
ARCHITECTURE beha io OF cla_bcd2

3_ b_ hd IS

-- Componen Decla a ion fo he Uni Unde Te

COMPONENT CLA_BCD2XS3
PORT(
X : IN d_logic_ ec o (3 do n o 0);
Y : OUT d_logic_ ec o (4 do n o 0)
);
END COMPONENT;

(UUT)

--Inp
SIGNAL X :

d_logic_ ec o (3 do n o 0) := (o he =>'0');

--O p
SIGNAL Y :

d_logic_ ec o (4 do n o 0);

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BEGIN
-- In an ia e he Uni Unde Te (UUT)
: CLA_BCD2XS3 PORT MAP(
X => X,
Y => Y
);
b : PROCESS
BEGIN
-- Wai 100 n fo global e e o fini h
ai fo 100 n ;
-- Place

im l

he e

X<="0101";
ai fo 50 n ;
X<="0111";
ai fo 50 n ;
X<="1011";
ai fo 50 n ;
ai ; -- ill ai fo e e
END PROCESS;
END;

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