Criando um projeto

para a placa Basys 2

Programar a seguinte tabela

A
P11
0
0
1
1
S= /A/B + A/B
S = /B

B
L3
0
1
0
1

S
M5
1
0
1
0

Fluxo de Dados Data Flow

1. Passo 1 Sintetizar
2. Passo 2 Implementar

Comportamental Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity funcao00 is
port (A : in
std_logic;
B : in
std_logic;
S : out std_logic);
end funcao00;
--architecture data_flow of funcao00 is
-- begin
-- S <= (not(A) and not(B)) or (A and not(B));
--end architecture;
architecture behavioral of funcao00 is
begin
func : process(a,b)
begin
if (a='0' and b='0') then
S <= '1';
elsif (a='0' and b='1') then
S <= '0';
elsif (a='1' and b='0') then
S <= '1';
else
S <= '0';
end if;
end process func;
end architecture behavioral;

Diagrama em Blocos

Simulao

Boto direito no sinal :

Exemplos de Cdigo
http://www.quicknet.se/hdc/hdl/educaton/mux4_1/
--

=============================================================================
-- file name is: mux4_1.vhd
(mux=multiplexer)
-- Author:
Kim Petersen
-- Created:
00.04.10
last modified: 00.04.13
-- =============================================================================
-- It is a 4 input multiplexer with the function as:
-sel
Input => output
comments
-MSB LSB
-0
0
in0 => output
-0
1
in1 => output
-1
0
in2 => output
-1
1
in3 => output
---------IF
and CASE can only be used inside a process.
-WHEN and WITH can only be used outside a process.
--IF
corresponds to WHEN
-CASE correpsonds to WITH
-- =============================================================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY mux4_1 IS
PORT (s0
s1
in0
in1
in2
in3
output
);
END mux4_1;

:
:
:
:
:
:
:

IN
IN
IN
IN
IN
IN
OUT

-- can be different dependent on tool used.

-- can be different dependent on tool used.
STD_LOGIC;
STD_LOGIC;
STD_LOGIC;
STD_LOGIC;
STD_LOGIC;
STD_LOGIC;
STD_LOGIC

-- =============================================================================
ARCHITECTURE if_example OF mux4_1 IS
BEGIN
mux:PROCESS(s0, s1, in0, in1, in2, in3)
BEGIN
IF

(s0='0' AND s1='0') THEN

output <= in0;
ELSIF (s0='1' AND s1='0') THEN
output <= in1;
ELSIF (s0='0' AND s1='1') THEN
output <= in2;
ELSIF (s0='1' AND s1='1') THEN
output <= in3;
ELSE
-- (s0 or s1 are not 0 or 1)
output <= 'X';
END IF;
END PROCESS mux;
END if_example;

ARCHITECTURE case_example OF mux4_1 IS

BEGIN
mux:PROCESS(s0, s1, in0, in1, in2, in3)
VARIABLE sel : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
sel := s1 & s0;
-- concatenate s1 and s0
CASE sel IS
WHEN "00"
WHEN "01"
WHEN "10"
WHEN "11"
WHEN OTHERS
END CASE;

=>
=>
=>
=>
=>

output
output
output
output
output

<=
<=
<=
<=
<=

in0;
in1;
in2;
in3;
'X';

END PROCESS mux;

END case_example;
-- =============================================================================
ARCHITECTURE with_example OF mux4_1 IS
SIGNAL

sel

STD_LOGIC_VECTOR(1 DOWNTO 0);

BEGIN
sel <= s1 & s0; -- concatenate s1 and s0
WITH sel SELECT
output <= in0 WHEN "00",
in1 WHEN "01",
in2 WHEN "10",
in3 WHEN "11",
'X' WHEN OTHERS;
END with_example;
-- =============================================================================
ARCHITECTURE when_example OF mux4_1 IS
BEGIN
output <= in0 WHEN
in1 WHEN
in2 WHEN
in3 WHEN
'X';
END when_example;

(s1
(s1
(s1
(s1

&
&
&
&

s0)="00"
s0)="01"
s0)="10"
s0)="11"

ELSE
ELSE
ELSE
ELSE