FILKOM | UB

CCE61206

Pemrograman FPGA
Agenda

• Introduction
• Review Sistem Digital
• FPGA design dengan Xilinx
• Rangkaian kombinasional
• Rangkaian Enkoder, Decoder, Multiplekser dll
• Konsep-konsep tambahan dalam pemrograman
• Flip flop
• -----------------------------------UTS-------------------------------------
• Rangkaian Counter
• Materi pengayaan
• Desain project dan presentasi
• -----------------------------------UAS-------------------------------------

Slide 2
26 October 2020
process

Slide 3
26 October 2020
More on process
1. multiple processes interact with each other just like concurrent statements – concurrently.
They can be accessed using sensitivity list

Use sensitivity list or

wait statements
(but NOT both)

2. A PROCESS without a sensitivity list is defined to be an infinite loop. When the execution
reaches the bottom (end of the process), it automatically starts to execute again from the
begining. It suspends on on WAIT statements.

3. The value of a signal is updated only at the time when the PROCESS suspends!
The one without the sensitivity list suspends when it executes a WAIT statement while the one
with the list suspends at the end of the PROCESS automatically

Slide 4
26 October 2020
Signal and variable

i0 or not i1

i0 and i1

Declared as port

Can be written in 2 ways:

eq=(i0 or not i1) or (i0 and i1); p0= i0 or not i1;

Inside
p1= i0 and i1;
process
eq=p0 or p1;

Slide 5
But since p0 and p1 are not ports, it has to be declared as signal or variable
26 October 2020
 Signal VS variable

...
signal x,y,z : bit; process (y)
... variable x,z : bit;
process (y) begin
begin x:=y;
x<=y; z:=not x;
z<=not x; end process;
end process;

• Declared OUTSIDE process • Declared INSIDE process

• Executed once the process completed • Value is updated immediately
• Value assignment using <= • Value assignment using :=
Signal VS variable
--------------------------------------------------------
-- Signal vs. Variable (sig_var.vhd)
-- Look at the outputs in simulation waveform
-- for same computation, we get two different results
--------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity sig_var is
port( d1, d2, d3: in std_logic;
res1, res2: out std_logic);
end sig_var;

architecture behv of sig_var is

signal sig_s1: std_logic;
begin
proc1: process(d1,d2,d3)
variable var_s1: std_logic;

begin
var_s1 := d1 and d2;
res1 <= var_s1 xor d3;
end process;

proc2: process(d1,d2,d3)
begin
sig_s1 <= d1 and d2;
res2 <= sig_s1 xor d3;
end process;
end behv;
WAIT STATEMENT (1)
WAIT FOR ;

This causes the process to re-execute after a specific amount of time has
passed.
As we have used earlier, this can be useful in writing test benches to create
stimulus where signals are required to change value over time.

Example:

stimulus: PROCESS
BEGIN
sel <= '0';
bus_a <= "1111";
bus_b <= "0000";
WAIT FOR 10 ns;
sel <= '1';
WAIT FOR 10 ns;
-- .....
END PROCESS stimulus;
WAIT STATEMENT (2)

WAIT ON ;

The WAIT ON statement waits for an event on one or more of the signals in
a list specified before re-executing.

PROCESS
BEGIN
IF (a='1' OR b='1') THEN z <= '1';
ELSE z <= '0';
END IF;
WAIT ON a, b;
END PROCESS;
WAIT STATEMENT (3)
WAIT UNTIL ;

The WAIT UNTIL statement has a condition which returns either TRUE or
FALSE.
The statement waits for an event on one of the signals in the condition, and
if as a result of the event the condition has become true, then the process
re-executes.

PROCESS
BEGIN
WAIT UNTIL clk='1';
q <= d;
END PROCESS;
WAIT STATEMENT (4)
WAIT;

Lastly, it is possible to just use WAIT to suspend a process forever. You may
ask, what is the usage of this structure? Well, it can be used in a test bench to
make sure your infinite loop feature of the processes from causing your
stimulus to repeat once complete.

stimulus: PROCESS
BEGIN
sel <= '0';
bus_a <= "1111";
bus_b <= "0000";
WAIT FOR 10 ns;
sel <= '1';
WAIT;
END PROCESS stimulus;
CONCATENATION
The & operator is a built-in VHDL operator that performs the concatenation
of bit_vectors. For example, with the following declarations:

signal a: bit_vector (3 downto 0);

signal b: bit_vector (7 downto 0);

The following statement would connect a to the right half of b and make the
left half of b constant “0000”'.

a<=“1010”
b<="0000" & a;

The & appends the a to the end of the "0000" to form a result that contains
8 bits.

b value is = 00001010
Std_logic_vector

(7 downto 0)
11010011
MSB LSB
a(7) a(0)

Slide 13
26 October 2020
 LOOPING

signal x : bit_vector (7 downto 0);

MEANS:
...
p:='0';
process (x)
p:=p xor x(7);
variable p : bit;
p:=p xor x(6);
begin
p:=p xor x(5);
p:='0‘;
p:=p xor x(4);
for i in 7 downto 0 loop
p:=p xor x(3);
p:=p xor x(i);
p:=p xor x(2);
end loop;
p:=p xor x(1);
end process;
p:=p xor x(0);

Loop from 7 to 0, but if need 0 to 7 then:

FOR i IN 0 TO 7 LOOP
Component (1)
we can divide the code in to sub modules as component and combine them
using Port Map technique.

Slide 15
26 October 2020
Component (2)
Example:

Slide 16
26 October 2020
Component (3)
Mux 2 to 1, in: (x,y) selector:(s) out:(z)

Slide 17
26 October 2020
Component (4)

Slide 18
26 October 2020
Constant and generic

Slide 19
26 October 2020
Data type and Operator

Slide 20
Type casting

26 October 2020
 PlanAhead
drive strength (output) dan pull type (input) untuk seluruh port input dan output yang terdefinisi

▪ drive strength adalah set minimum arus yang disediakan (mA)

▪ pull type adalah penambahan pull-up atau pull-down pada pin FPGA.
▪ Untuk slider switch, Pull-up sebenarnya bersifat opsional, namun disarankan
agar input tetap terdefinisi ketika switch berada di tengah transisi antara on
dan off. Ketika switch berada di ON, FPGA pin terkoneksi ke logic high
sedangkan ketika posisi OFF, FPGA pin terkoneksi ke ground.
▪ Untuk push button, pull-down resistor diperlukan untuk memberikan logic
low (ground) ketika tombol tidak ditekan [Spartan 3E User Guide]

Slide 21
▪ Secara default, I/O std adalah LVCMOS25 dengan SLOW slewrate dan output
drive 12 mA
26 October 2020