CS 310 University of Texas

CS 310 University of Texas

Introduction to Addressing Modes

Addressing Mode (definition):
The strategy to identify WHERE the operand is located. Note1: each addressing mode has a unique formula to locate the operand. Note2: The operand is in memory in all (but 2) addressing modes

Example Addressing Modes for accessing Data

ADDRESSING MODE (Direct) Register Immediate Register Indirect Base + Offset {aka Register Indirect with offset/displacement} Direct Memory (aka Absolute) PC-Relative Memory Indirect EFFECTIVE ADDRESS FORMULA Operand is in Register Operand is in Instruction E.A. = Contents(Register) E.A. = Contents(Base Register) + sign ext (offset) Mem Access ? NO NO YES YES LC-3 ? YES YES YES YES RISC ISAs ? ALL ALL ALL, via Base and Offset = 0 ALL

Effective Address (definition):

Actual location of operand to be used by the instruction:

E.A. = <address in instruction> E.A. = Contents(PC) + sign ext (offset) E.A. = Contents(MEMORY[X]), where in LC-3, X is calculated as: Contents(PC) + sign ext (offset) E.A. = Contents(Base Register) + Contents(Index Register) E.A. = Contents(Base Register), AND increments the contents of the Base Register by SIZE of the operand

YES YES YES

NO YES YES

How does each type of instruction use effective addr?

load type instr: store type instr: jump type instr: copy eff. addr type instr: ALU type instr (Intel ISA) Rdest ! Mem[eff.addr] Mem[eff.addr] ! Rsrc PC ! effective address Rdest ! effective address Rdest ! Rsrc + Mem[eff.addr] AddrModes-1

ALL, via Base = 0 and Offset = small addr YES NO, too complex SOME SOME

Indexed Register Indirect with auto increment Others ..

YES YES

NO NO

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(Direct) Register Addressing Mode

Memory Addressing Mode? No Effective Address: operand is located in specified reg # LC-3 syntax: Rn, where 0 ! n ! 7 Generic RISC syntax: Rn, where 0 ! n ! 31 Intel syntax: EAX, EBX, . Usage:
For permanent location of scalar variables For temporary calculations of any data or addresses

Immediate Addressing Mode

Memory Addressing Mode? No Effective Address: operand located in the INSTRUCTION LC-3 syntax: #<decimal digits>, x<hex digits>, b<bits> Generic syntax: #<digits> (or symbolic name of a constant) Intel syntax: <decimal digits> for 8/16/32bit constants Usage:
For any compile-time or assembly-time constants Modern ISAs have a limited # of bits for the operand, e.g. 10-16

Popularity: In ISAs that are not a RISC Load/Store ISA, this addressing mode is used for 50% of operand references

Popularity: (3rd) In ISAs that are not a RISC Load/Store ISA, this addressing mode is used for (9-20%) of operand references.
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Register Indirect Addressing Mode

Memory Addressing Mode? Yes Effective Address: contents(Register <n>) LC-3 syntax: can be modelled with Base + offset of zero plus: JMP R7, JSRR R3 Generic syntax: (R<n>) Usage: accessing a pointer or a computed address
Most basic memory addressing mode to access any type of data Particularly important for locations that must be calculated at run-time

Base + Offset Addressing Mode

Memory Addressing Mode? Yes Effective Address: contents(Register <n>) + sign ext(offset, that is known at compile/assembly time) LC-3 syntax: R<n>, <numeric offset> Generic syntax: <numeric displacement>(R<n>) Usage: very versatile
Models the register indirect addressing mode with an offset of 0 Allows non-zero offsets, useful in structures, class data members, and the run-time stack (used for function calls & static local variables)

Popularity: (4th) In ISAs that are not a RISC Load/Store ISA, this addressing mode is used for (2-12%) of operand references.

Popularity: (2nd) In ISAs that are not a RISC Load/Store ISA, this addressing mode is used for (16-27%) of operand references.
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Statistics on Base + Offset Mode

Size of offset (aka displacement) is an issue
Large size requires more bits in instruction

Absolute Addressing Mode

Memory Addressing Mode? Yes Effective Address: address stored in instruction, must be known at compile time) LC-3 syntax: not used Generic syntax: LOAD Rdst, <symbolic name or value> Typical Usage: Global variables, OS programming

Statistics for Alpha architecture with full optimization for SPEC CPU2000

Log2(displacement)

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PC Relative Addressing Mode

Memory Addressing Mode? Yes Effective Address: contents(PC) + sign ext(offset, that is known at compile/assembly time) LC-3 syntax: label used with LD, ST, LEA, BR, JSR (example: JSR LShift) Generic usage: typical usage for branching to a label ( i.e. commonly used to reference instructions NOT data!!!) Why do compilers not use PC-relative for data???

PC-relative Addressing Mode Example

Example

Assembly Time:

Run-Time (fetch phase) Run-Time (fetch operands phase)

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LD (PC-Relative)

LEA (Immediate) NO, its PC-Relative!!!

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PC-Relative Limitations Example

1) PROBLEM: ST R3, ABC .. far ABC .BLKW 1 ;IF the ST instruction is TOO FAR from ABC, ;(assume ABC is a scalar value) ;an assembly time error would occur (in pass2)

Memory Indirect Addressing Mode

Memory Addressing Mode? Yes Effective Address: contents( Mem[ PC + sign ext(offset)] ) LC-3 syntax: indicated by LDI & STI mnemonics & label Other ISAs defines it as: contents (Mem[ Regs[Rsrc]]) Usage:
Goal: access a single-valued (scalar) variable that is too far from the instruction Technique: Create a memory pointer that is near the instruction, using the allocate/initialize assembler directive (e.g. LC-3s .FILL)

2) SOLUTION: Create a memory pointer that is NEAR to the instruction; This memory pointer contains the address of ABC. LD R0, ABC_PTR ;R0 contains the address of ABC STR R3, R0, 0 ;R3 is stored into ABC near ABC_PTR .FILL ABC ; note, that there is no constraint of the ; distance between the ABC_PTR & ABC, ... far ; they just have to be in same source file ABC .BLKW 1 ; a scalar variable ... AddrModes-13

Popularity: (6th out of 6) In ISAs that are not a RISC Load/Store ISA, this addressing mode is used for (0.5-3%) of operand references.
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Memory Pointer Example (using memory indirect)

Given the problem that ABC and the STI instruction are too far apart, we have already seen a solution that requires 2 instructions. We can avoid one of the 2 instructions by using the Memory Indirect addressing mode STI R3, ABC_PTR ; The value of R3 is now stored into ABC ... ;assuming the distance from the STI instr ... ; to ABC_PTR fits in the 9bit offset field. ABC_PTR .FILL ABC ; note, that there is no constraint of the ; distance between the ABC_PTR & ABC, ... ; they just have to be in same source file ABC .BLKW 1 ; a scalar variable ...

Additional Example (for arrays/structures)

1) Assume HEAP and the LD instruction are too far apart, thus an assembly time error would occur (since the PC offset to HEAP exceeds the # of bits in the instruction for the offset). 2) Solution: Create a memory pointer pointing to HEAP (an array) but we wont be able to use Memory Indirect LD R1, HEAP_PTR ; R1 now contains the address of HEAP ; assuming that the distance between ;HEAP_PTR and the LD instruction fits ... LDR R2, R1, #1 ; R2 contains the value of the 2nd word ... ; of the HEAP data structure HEAP_PTR .FILL HEAP ; note, that there is no constraint of the ... ; distance between HEAP_PTR & HEAP HEAP .BLKW x1000 ; declaration of an array or structure ... AddrModes-16

NOTE: the memory indirect mode is not a solution for typical accesses to arrays or structures, so we must use the original solution.
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LDI (Memory Indirect)

STI (Memory Indirect)

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