FSW25N50A

N-Channel MOSFET Pb Lead Free Package and Finish

Applications:
• Uninterruptible Power Supply(UPS) VDSS RDS(ON) (Typ.) ID
• LCD Panel Power
• SMPS Power
500V 0.18 : 25A
• DC-AC Inverter

FSW25N50
• RoHS Compliant
• Low ON Resistance
• Low Gate Charge
• Peak Current vs Pulse Width Curve
• ESD Capability Improved G
D
S
Ordering Information
PART NUMBER PACKAGE BRAND TO-3PN
FSW25N50A TO-3PN FSW25N50A Not to Scale

Absolute Maximum Ratings TC=25 oC unless otherwise specified

Symbol Parameter FSW25N50A Units
VDSS Drain-to-Source Voltage (NOTE *1) 500 V
ID Continuous Drain Current 25
o
ID@ 100 C Continuous Drain Current Figure 3 A
IDM Pulsed Drain Current, VGS@ 10V (NOTE *2) Figure 6
Power Dissipation 230 W
PD o o
Derating Factor above 25 C 1.84 W/ C
VGS Gate-to-Source Voltage ± 30 V
Single Pulse Avalanche Engergy
EAS 2500 mJ
L=10mH
IAS Pulsed Avalanche Rating Figure 8
dv/dt Peak Diode Recovery dv/dt (NOTE *3) 5.0 V/ns
VESD(G-S) Gate to Source ESD:HBM_C=100pF,R=1.5K: 6000 V
Maximum Temperature for Soldering
TL Leads at 0.063in (1.6mm) from Case for 10 seconds 300 o
TPKG Package Body for 10 seconds 260 C

TJ and TSTG Operating Junction and Storage Temperature Range -55 to 150
*Drain Current limited by Maximum Junction Temperature.
Caution: Stresses greater than those listed in the “Absolute Maximum Ratings” Table may cause permanent damage to the device.

Thermal Resistance
Symbol Parameter FSW25N50A Units Test Conditions
Water cooled heatsink, PD adjusted for
RTJC Junction-to-Case 0.54 o
o
C/W a peak junction temperature of +150 C.
RTJA Junction-to-Ambient 62 1 cubic foot chamber, free air.

©2011 InPower Semiconductor Co., Ltd. Page 1 of 9 FSW25N50A REV. A Jan. 2011
 o
OFF Characteristics TJ=25 C unless otherwise specified
Symbol Parameter Min. Typ. Max. Units Test Conditions
BVDSS Drain-to-Source Breakdown Voltage 500 -- -- V VGS=0V, ID=250μA
o
BreakdownVoltage Temperature Reference to 25 C,
'BVDSS /' TJ -- 0.60 -- o
V/ C
Coefficient, Figure 11. ID=250μA

-- -- 10 VDS=500V, VGS=0V
IDSS Drain-to-Source Leakage Current μA
-- -- VDS=400V, VGS=0V
250 o
TJ=125 C
Gate-to-Source Forward Leakage -- -- +10 VGS=+30V
IGSS uA
Gate-to-Source Reverse Leakage -- -- -10 VGS= -30V

ON Characteristics TJ=25 oC unless otherwise specified

Symbol Parameter Min. Typ. Max. Units Test Conditions
Static Drain-to-Source On-Resistance VGS=10V, ID=10A
RDS(ON) -- 0.18 0.26 :
Figure 9 and 10. (NOTE *4)
VGS(TH) Gate Threshold Voltage, Figure 12. 2.0 -- 4.0 V VDS=VGS, ID=250PA

gfs Forward Transconductance 24 VDS=15V, ID=10A

-- -- S
(NOTE *4)

Dynamic Characteristics Essentially independent of operating temperature

Symbol Parameter Min. Typ. Max. Units Test Conditions
Ciss Input Capacitance -- 4900 -- VGS=0V
Coss Output Capacitance -- 410 -- VDS=25V
pF
f =1.0MHz
Crss Reverse Transfer Capacitance -- 44 --
Figure 14
Qg Total Gate Charge -- 96 -- VDD=250V
ID=20A
Qgs Gate-to-Source Charge -- 18 -- nC
VGS=10 V
Qgd Gate-to-Drain (“Miller”) Charge -- 41 -- Figure 15

Resistive Switching Characteristics Essentially independent of operating temperature

Symbol Parameter Min. Typ. Max. Units Test Conditions
td(ON) Turn-on Delay Time -- 53 -- VDD=250V
trise Rise Time -- 117 -- ID=20A
ns
td(OFF) Turn-Off Delay Time -- 307 -- VGS=10V
tfall Fall Time -- 138 -- RG=25:

©2011 InPower Semiconductor Co., Ltd. Page 2 of 9 FSW25N50A REV. A Jan. 2011
 o
Source-Drain Diode Characteristics Tc=25 C unless otherwise specified
Symbol Parameter Min. Typ. Max. Units Test Conditions
IS Continuous Source Current (Body Diode) -- -- 25 A Integral pn-diode
ISM Maximum Pulsed Current (Body Diode) -- -- 100 A in MOSFET
VSD Diode Forward Voltage -- -- 1.5 V IS=20A, VGS=0V
trr Reverse Recovery Time -- 558 -- ns VGS=0V
Qrr Reverse Recovery Charge -- 6.1 -- μC IF=20A, di/dt=100 A/μs

Notes:

*1. TJ = +25 oC to +150 oC.

*2. Repetitive rating; pulse width limited by maximum junction temperature.
*3. ISD= 20A di/dt < 100 A/μs, VDD < BVDSS, TJ=+150 oC.
*4. Pulse width < 380μs; duty cycle < 2%.

©2011 InPower Semiconductor Co., Ltd. Page 3 of 9 FSW25N50A REV. A Jan. 2011
 Duty Factor Figure 1. Maximum Effective Thermal Impedance, Junction-to-Case
1.000
50%

20%
ZTJC, Thermal Impedance

10%
0.100 PDM
5%
(Normalized)

2% t1
t2
1%
0.010 NOTES:
single pulse DUTY FACTOR: D=t1/t2
PEAK TJ=PDM x ZTJC x RTJC+TC

0.001

1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01

tp, Rectangular Pulse Duration (s)

Figure 2. Maximum Power Dissipation Figure 3. Maximum Continuous Drain Current

vs Case Temperature vs Case Temperature
250 25
PD, Power Dissipation (W)

200 20
ID, Drain Current (A)

150 15

100 10

50
5

0 0

25 50 75 100 125 150 25 50 75 100 125 150

o o
TC, Case Temperature ( C) TC, Case Temperature ( C)

Figure 4. Typical Output Characteristics Figure5. Typical Drain-to-Source ON Resistance

vs Gate Voltage and Drain Current

75 1.5
PULSE DURATION = 250 μS PULSE DURATION = 250 μS
V
DUTY FACTOR = 0.5% MAX
GS
= 15 DUTY FACTOR = 0.5% MAX
V
RDS(ON), Drain-to-Source

o
TC = 25 C 1.25 TC = 25 oC
60 6.0V
VGS =
ID, Drain Current (A)

ON Resistance (:

1.0 ID = 20A
45 VGS = 5.5V ID = 10A
0.75
VGS = 5.25V
30
VGS = 5.0V 0.5

15 0.25
VGS = 4.5V

0 0
0 5 10 15 20 25 30 4 5 6 7 8 9 10 11 12 13 14 15

VDS, Drain-to-Source Voltage (V) VGS, Gate-to-Source Voltage (V)

©2011 InPower Semiconductor Co., Ltd. Page 4 of 9 FSW25N50A REV. A Jan. 2011
 Figure 6. Maximum Peak Current Capability
1000
TRANSCONDUCTANCE FOR TEMPERATURES
MAY LIMIT CURRENT IN
ABOVE 25 oC DERATE PEAK
THIS REGION
CURRENT AS FOLLOWS:
IDM, Peak Current (A)

, = ,   – 7 &-
--------------------
100 

10

VGS = 10V
1
1E-6 10E-6 100E-6 1E-3 10E-3 100E-3 1E+0 10E+0

tp, Pulse Width (s)

Figure 7. Typical Transfer Characteristics Figure 8. Unclamped Inductive

Switching Capability
45 1000
PULSE DURATION = 250 μs
ID, Drain-to-Source Current (A)

DUTY CYCLE = 0.5% MAX

VDS = 10 V
IAS, Avalanche Current (A)

37.5

30 100.

22.5 STARTING TJ = 25 oC
STARTING TJ = 150 oC

15 10.0
+150 oC
+25 oC If R= 0: tAV= (L×IAS)/(1.3BVDSS-VDD)
7.5
-55 oC If Rz 0: tAV= (L/R) ln[IAS×R)/(1.3BVDSS-VDD)+1]
R equals total Series resistance of Drain circuit
0 1.00
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 1E-6 10E-6 100E-6 1E-3 10E-3 100E-3

VGS, Gate-to-Source Voltage (V) tAV, Time in Avalanche (s)

Figure 9. Typical Drain-to-Source ON Figure 10. Typical Drain-to-Source ON Resistance

Resistance vs Drain Current vs Junction Temperature
0.75 2.6
PULSE DURATION = 2 μs 2.4
DUTY CYCLE = 0.5% MAX
RDS(ON), Drain-to-Source
RDS(ON), Drain-to-Source

2.2
Resistance (Normalized)

0.60 TC=25°C
2.0
ON Resistance (:)

V = 10V
GS 1.8
0.45 1.6
V = 20V 1.4
GS
0.30 1.2
1.0
0.8
0.15 PULSE DURATION = 250 μs
0.6
DUTY CYCLE = 0.5% MAX
0.4 VGS = 10V, ID = 10.0A
0 0.2
0 5 10 15 20 25 30 -75 -50 -25 0 25 50 75 100 125 150

ID, Drain Current (A) TJ, Junction Temperature (oC)

©2011 InPower Semiconductor Co., Ltd. Page 5 of 9 FSW25N50A REV. A Jan. 2011
 Figure 11. Typical Breakdown Voltage vs Figure 12. Typical Threshold Voltage vs
Junction Temperature Junction Temperature
1.15 1.2
Breakdown Voltage (Normalized)

VGS(TH), Threshold Voltage

BVDSS, Drain-to-Source

1.10 1.1

(Normalized)
1.05 1.0

1.00 0.9

0.95 0.8
VGS = 0V VGS = VDS
ID = 250 μA ID = 250 μA
0.90 0.7
-75 -50 -25 0.0 25 50 75 100 125 150 -75 -50 -25 0.0 25 50 75 100 125 150
o o
TJ, Junction Temperature ( C) TJ, Junction Temperature ( C)

Figure 13. Maximum Forward Bias Safe Figure 14. Typical Capacitance vs
Operating Area
1000 10000
TJ = MAX RATED, TC = 25 oC
Single Pulse
10μs
100
1000 Ciss
C, Capacitance (pF)
ID, Drain Current (A)

10
0μ
s
10 1.
0m
s
10 100 Coss
m
s
1.0
DC
VGS = 0V, f = 1MHz Crss
10 Ciss = Cgs + Cgd
0.1
OPERATION IN THIS AREA MAY Coss # Cds + Cgd
BE LIMITED BY R
DS(ON) Crss = Cgd
0.01 1
1 10 100 1000 0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V) VDS, Drain Voltage (V)

Figure 15. Typical Gate Charge Figure 16. Typical Body Diode Transfer
vs Gate-to-Source Voltage Characteristics
12 50
VGS, Gate-to-Source Voltage (V)

ISD, Reverse Drain Current (A)

45
10
40
VDS = 125V
VDS = 250V 35
8
VDS = 375V 30
6 25
20
4 +150 oC
15 o
+25 C
2 10
-55 oC
ID = 10A 5 VGS = 0V
0 0
0 20 40 60 80 100 0.4 0.6 0.8 1.0 1.2 1.4 1.6

QG , Total Gate Charge (nC) VSD, Source-to-Drain Voltage (V)

©2011 InPower Semiconductor Co., Ltd. Page 6 of 9 FSW25N50A REV. A Jan. 2011
 Test Circuits and Waveforms

VDS
ID
ID
VDS VGS
Miller
Region
VGS
VDD
D.U.T.
VGS(TH)

1 mA
Qgs Qgd
Qg

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveform

VDS
RL 90%
VDS

VGS
VDD
RG D.U.T.
10%
VGS

td(ON) trise td(OFF) tfall

Figure 19. Resistive Switching Test Circuit Figure 20. Resistive Switching Waveforms

©2011 InPower Semiconductor Co., Ltd. Page 7 of 9 FSW25N50A REV. A Jan. 2011
 Test Circuits and Waveforms

di/dt adj. Current

Pump

di/dt = 100A/μA
ID
Double Pulse

D.U.T. VDD
Qrr
L
trr

ID

Figure 22. Diode Reverse Recovery Waveform

Figure 21. Diode Reverse Recovery Test Circuit

BVDSS

Series Switch
(MOSFET)
L
IAS

BVDSS

D.U.T. VDD VDD

Commutating
Diode
0 tAV

VGS 50:
IAS
VGS tp

I AS 2 L
E AS
2

Figure 23. Unclamped Inductive Switching Test Circuit Figure 24. Unclamped Inductive Switching Waveforms

©2011 InPower Semiconductor Co., Ltd. Page 8 of 9 FSW25N50A REV. A Jan. 2011
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