FTP11N08A

N-Channel MOSFET Pb Lead Free Package and Finish

Applications:
• Automotive VDSS RDS(ON) (Max.) ID
• DC Motor Control
• Class D Amplifier 75V 11 m: 100A

Features:
• RoHS Compliant D
• Low ON Resistance
• Low Gate Charge
• Peak Current vs Pulse Width Curve
• Inductive Switching Curves
G G
D
Ordering Information S
TO-220
PART NUMBER PACKAGE BRAND Not to Scale S
FTP11N08A TO-220 FTP11N08A

Absolute Maximum Ratings TC=25 oC unless otherwise specified

Symbol Parameter FTP11N08A Units
VDSS Drain-to-Source Voltage (NOTE *1) 75 V
ID Continuous Drain Current 100*
o
ID@ 100 C Continuous Drain Current Figure 3 A
IDM Pulsed Drain Current, VGS@ 10V (NOTE *2) Figure 6
Power Dissipation 230 W
PD o o
Derating Factor above 25 C 1.54 W/ C
VGS Gate-to-Source Voltage ± 20 V
Single Pulse Avalanche Engergy
EAS 600 mJ
L=10 mH, ID=11 Amps
IAS Pulsed Avalanche Rating Figure 8
dv/dt Peak Diode Recovery dv/dt (NOTE *3) 5.0 V/ns
Maximum Temperature for Soldering
o
TL Leads at 0.063in (1.6mm) from Case for 10 seconds 300 C
TPKG Package Body for 10 seconds 260
Operating Junction and Storage
TJ and TSTG -55 to 175
Temperature Range

*Drain Current limited by Maximum Package Current Rating, 75 Amps

Caution: Stresses greater than those listed in the “Absolute Maximum Ratings” Table may cause permanent damage to the device.

Thermal Resistance
Symbol Parameter Min. Typ. Max. Units Test Conditions
Water cooled heatsink, PD adjusted for
RTJC Junction-to-Case -- -- 0.65 o
o
C/W a peak junction temperature of +175 C.
RTJA Junction-to-Ambient -- -- 62 1 cubic foot chamber, free air.

©2009 InPower Semiconductor Co., Ltd. Page 1 of 9 FTP11N08A REV. A Apr. 2009
 o
OFF Characteristics TJ=25 C unless otherwise specified
Symbol Parameter Min. Typ. Max. Units Test Conditions
BVDSS Drain-to-Source Breakdown Voltage 75 -- -- V VGS=0V, ID=250μA
o
BreakdownVoltage Temperature Reference to 25 C,
'BVDSS /' TJ -- -- o
V/ C
Coefficient, Figure 11. 0.08 ID=250μA

-- -- 25 VDS=75V, VGS=0V
IDSS Drain-to-Source Leakage Current μA
VDS=60V, VGS=0V
-- -- 250 o
TJ=150 C
Gate-to-Source Forward Leakage -- -- 100 VGS=+20V
IGSS nA
Gate-to-Source Reverse Leakage -- -- -100 VGS= -20V

ON Characteristics TJ=25 oC unless otherwise specified

Symbol Parameter Min. Typ. Max. Units Test Conditions
Static Drain-to-Source On-Resistance VGS=10V, ID=45A
RDS(ON) -- 9.5 11.0 m:
Figure 9 and 10. (NOTE *4)
VGS(TH) Gate Threshold Voltage, Figure 12. 2.0 -- 4.0 V VDS=VGS, ID=250PA
VDS=15V, ID=75A
gfs Forward Transconductance -- 83 -- S
(NOTE *4)

Dynamic Characteristics Essentially independent of operating temperature

Symbol Parameter Min. Typ. Max. Units Test Conditions
Ciss Input Capacitance -- 4541 -- VGS=0V
Coss Output Capacitance -- 717 -- VDS=25V
pF
f =1.0MHz
Crss Reverse Transfer Capacitance -- 40 --
Figure 14
Qg Total Gate Charge -- 69 -- VDD=37V
ID=75A
Qgs Gate-to-Source Charge -- 16 -- nC
VGS=10 V
Qgd Gate-to-Drain (“Miller”) Charge -- 24 -- Figure 15

Resistive Switching Characteristics Essentially independent of operating temperature

Symbol Parameter Min. Typ. Max. Units Test Conditions
td(ON) Turn-on Delay Time -- 17 -- VDD=30V
trise Rise Time -- 57 -- ID=75A
ns
td(OFF) Turn-Off Delay Time -- 57 -- VGS=10V
tfall Fall Time -- 34 -- RG=4.7:

©2009 InPower Semiconductor Co., Ltd. Page 2 of 9 FTP11N08A REV. A Apr. 2009
 o
Source-Drain Diode Characteristics Tc=25 C unless otherwise specified
Symbol Parameter Min. Typ. Max. Units Test Conditions
IS Continuous Source Current (Body Diode) -- -- 100 A Integral pn-diode
ISM Maximum Pulsed Current (Body Diode) -- -- 400 A in MOSFET
VSD Diode Forward Voltage -- -- 1.5 V IS=75A, VGS=0V
trr Reverse Recovery Time -- 89 134 ns VGS=0V
Qrr Reverse Recovery Charge -- 251 377 nC IF=75A, di/dt=100 A/μs

Notes:

*1. TJ = +25 oC to +175oC.

*2. Repetitive rating; pulse width limited by maximum junction temperature.
*3. ISD= 75A di/dt < 100 A/μs, VDD < BVDSS, TJ=+175oC.
*4. Pulse width < 380μs; duty cycle < 2%.

©2009 InPower Semiconductor Co., Ltd. Page 3 of 9 FTP11N08A REV. A Apr. 2009
 Duty Factor Figure 1. Maximum Effective Thermal Impedance, Junction-to-Case
1.000
50%

20%
ZTJC, Thermal Impedance

10%
0.100
5%
(Normalized)

2%
PDM

1% t1
0.010
single pulse t2
NOTES:
DUTY FACTOR: D=t1/t2
PEAK TJ=PDM x ZTJC x RTJC+TC
0.001

1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01

tp, Rectangular Pulse Duration (s)

Figure 2. Maximum Power Dissipation Figure 3. Maximum Continuous Drain Current

vs Case Temperature vs Case Temperature

250 80
PD, Power Dissipation (W)

225 70
ID, Drain Current (A)

200
60
175
Limited By Package
150 50

125 40
100 30
75
20
50
25 10

0 0
25 50 75 100 125 150 175 25 50 75 100 125 150 175
o o
TC, Case Temperature ( C) TC, Case Temperature ( C)

Figure 4. Typical Output Characteristics Figure 5. Typical Drain-to-Source ON Resistance

.
vs Gate Voltage and Drain Current

140 0.05
PULSE DURATION = 10 μS PULSE DURATION =10 μS
VGS = 15V DUTY FACTOR = 0.5% MAX DUTY FACTOR = 0.5% MAX
RDS(ON), Drain-to-Source

120 VGS = 10V TC = 25 oC TC = 25 oC

ID, Drain Current (A)

0.04
ON Resistance (:

VGS = 9V VGS = 8V
100

80 0.03 ID = 100A
ID = 50A
VGS = 7V
60 ID = 25A
0.02 ID = 12.5A
40 VGS = 6V
0.01
20 VGS = 5.5V
VGS = 5V
0 0.00
0 5 10 15 20 4 5 6 7 8 9 10 11 12 13 14 15

VDS, Drain-to-Source Voltage (V) VGS, Gate-to-Source Voltage (V)

©2009 InPower Semiconductor Co., Ltd. Page 4 of 9 FTP11N08A REV. A Apr. 2009
 Figure 6. Maximum Peak Current Capability

1000
IDM, Peak Current (A)

TRANSCONDUCTANCE
100 MAY LIMIT CURRENT IN
THIS REGION

FOR TEMPERATURES
ABOVE 25 oC DERATE PEAK
10 CURRENT AS FOLLOWS:

 –7
, = ,  --------------------&-
VGS = 10V 

1
10E-6 100E-6 1E-3 10E-3 100E-3 1E+0 10E+0
tp, Pulse Width (s)

Figure 7. Typical Transfer Characteristics Figure 8. Unclamped Inductive Switching

Capability
120 1000
PULSE DURATION = 10 μs
ID, Drain-to-Source Current (A)

DUTY CYCLE = 0.5% MAX

IAS, Avalanche Current (A)

100 TC=25°C

STARTING TJ = 25 oC
80 100

60
STARTING TJ = 150 oC
40 10
+175 oC
+25 oC
20 If R= 0: tAV= (L×IAS)/(1.3BVDSS-VDD)
-55 oC If Rz 0: tAV= (L/R) ln[IAS×R)/(1.3BVDSS-VDD)+1]
R equals total Series resistance of Drain circuit
0 1
3.0 4.0 5.0 6.0 7.0 8.0 1E-6 10E-6 100E-6 1E-3 10E-3

VGS, Gate-to-Source Voltage (V) tAV, Time in Avalanche (s)

Figure 9. Typical Drain-to-Source ON Figure 10. Typical Drain-to-Source ON Resistance

Resistance vs Drain Current vs Junction Temperature
0.018 2.00
PULSE DURATION = 10 μs
DUTY CYCLE = 0.5% MAX
RDS(ON), Drain-to-Source
RDS(ON), Drain-to-Source

1.75
Resistance (Normalized)

0.016 TC=25°C
ON Resistance (:)

1.50
0.014
1.25
0.012 V
GS
= 10V
1.00

0.010 PULSE DURATION = 10 μs

0.75
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 50A
0.008 0.50
0 25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 125 150 175

ID, Drain Current (A) TJ, Junction Temperature (oC)

©2009 InPower Semiconductor Co., Ltd. Page 5 of 9 FTP11N08A REV. A Apr. 2009
 Figure 11. Typical Breakdown Voltage vs Figure 12. Typical Threshold Voltage vs
Junction Temperature Junction Temperature
1.15 1.15
Breakdown Voltage (Normalized)

1.10

VGS(TH), Threshold Voltage

BVDSS, Drain-to-Source

1.10 1.05
1.00

(Normalized)
1.05 0.95
0.90
1.00 0.85
0.80
0.95 0.75
VGS = 0V VGS = VDS
ID = 250 μA
0.70
ID = 250 μA
0.90 0.65
-75 -50 -25 0.0 25 50 75 100 125 150 175 -75 -50 -25 0.0 25 50 75 100 125 150 175

TJ, Junction Temperature (oC) TJ, Junction Temperature (oC)

Figure 13. Maximum Forward Bias Safe Figure 14. Typical Capacitance vs
Operating Area Drain-to-Source Voltage

1000 10000
Ciss
10μs

100.0 100 Coss

C, Capacitance (pF)
ID, Drain Current (A)

μ
1000
1 ms
10.0
10m
s Crss
DC
OPERATION IN THIS AREA 100
MAY BE LIMITED BY R VGS = 0V, f = 1MHz
1.0 DS(ON)
Ciss = Cgs + Cgd
TJ = MAX RATED, TC = 25 oC Coss # Cds + Cgd
Single Pulse Crss = Cgd
0.1 10
1 10 100 0.1 1 10 100

VDS, Drain-to-Source Voltage (V) VDS, Drain Voltage (V)

Figure 15. Typical Gate Charge vs Gate-to- Figure 16. Typical Body Diode Transfer
Source Voltage Characteristics
12 150
VDS = 19V
VGS, Gate-to-Source Voltage (V)

ISD, Reverse Drain Current (A)

10 VDS = 37V 125

VDS = 56V

8 100
175 oC

6 75 o
25 C

4 50

2 25
ID = 75A VGS = 0V
0 0
0 10 20 30 40 50 60 70 80 90 100 0.2 0.4 0.6 0.8 1.0 1.2

QG , Total Gate Charge (nC) VSD, Source-to-Drain Voltage (V)

©2009 InPower Semiconductor Co., Ltd. Page 6 of 9 FTP11N08A REV. A Apr. 2009
Test Circuits and Waveforms

VDS
ID
ID
VDS VGS
Miller
Region
VGS
VDD
D.U.T.
VGS(TH)

1 mA
Qgs Qgd
Qg

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveform

VDS
RL 90%
VDS

VGS
VDD
RG D.U.T.
10%
VGS

td(ON) trise td(OFF) tfall

Figure 19. Resistive Switching Test Circuit Figure 20. Resistive Switching Waveforms

©2009 InPower Semiconductor Co., Ltd. Page 7 of 9 FTP11N08A REV. A Apr. 2009
 Test Circuits and Waveforms

di/dt adj. Current

Pump

di/dt = 100A/μA
ID
Double Pulse

D.U.T. VDD
Qrr
L
trr

ID

Figure 22. Diode Reverse Recovery Waveform

Figure 21. Diode Reverse Recovery Test Circuit

BVDSS

Series Switch
(MOSFET)
L
IAS

BVDSS

D.U.T. VDD VDD

Commutating
Diode
0 tAV

VGS 50:
IAS
VGS tp

I AS 2 L
E AS
2

Figure 23. Unclamped Inductive Switching Test Circuit Figure 24. Unclamped Inductive Switching Waveforms

©2009 InPower Semiconductor Co., Ltd. Page 8 of 9 FTP11N08A REV. A Apr. 2009
Disclaimers:
InPower Semiconductor Co., Ltd (IPS) reserves the right to make changes without notice in order to improve reliability,
function or design and to discontinue any product or service without notice. Customers should obtain the latest relevant
information before orders and should verify that such information is current and complete. All products are sold subject to
IPS’s terms and conditions supplied at the time of order acknowledgement.

InPower Semiconductor Co., Ltd warrants performance of its hardware products to the specifications at the time of sale,
Testing, reliability and quality control are used to the extent IPS deems necessary to support this warrantee. Except where
agreed upon by contractual agreement, testing of all parameters of each product is not necessarily performed.

InPower Semiconductor Co., Ltd does not assume any liability arising from the use of any product or circuit designs described
herein. Customers are responsible for their products and applications using IPS’s components. To minimize risk, customers
must provide adequate design and operating safeguards.

InPower Semiconductor Co., Ltd does not warrant or convey any license either expressed or implied under its patent rights,
nor the rights of others. Reproduction of information in IPS’s data sheets or data books is permissible only if reproduction is
without modification or alteration. Reproduction of this information with any alteration is an unfair and deceptive business
practice. InPower Semiconductor Co., Ltd is not responsible or liable for such altered documentation.

Resale of IPS’s products with statements different from or beyond the parameters stated by InPower Semiconductor Co., Ltd
for that product or service voids all express or implied warrantees for the associated IPS’s product or service and is unfair and
deceptive business practice. InPower Semiconductor Co., Ltd is not responsible or liable for any such statements.

Life Support Policy:

InPower Semiconductor Co., Ltd’s products are not authorized for use as critical components in life support devices or
systems without the expressed written approval of InPower Semiconductor Co., Ltd.

As used herein:
1. Life support devices or systems are devices or systems which:
a. are intended for surgical implant into the human body,
b. support or sustain life,
c. whose failure to perform when properly used in accordance with instructions
for used provided in the labeling, can be reasonably expected to result in significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

©2009 InPower Semiconductor Co., Ltd. Page 9 of 9 FTP11N08A REV. A Apr. 2009