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ISA10N80A

N-Channel MOSFET Pb Lead Free Package and Finish

Applications:
• ATX Power VDSS RDS(on)(Typ) ID (Max)
• LCD Panel Power
800V 0.8Ÿ 10A

Features:
• RoHS Compliant & Halogen Free
• Low ON Resistance
• Low Gate Charge G
D TO-220F
S
• ESD Capability Improved
Packages
Not to Scale
Ordering Information
Part Number Package Type Brand
ISA10N80A TO-220F IPS

Absolute Maximum Ratings Tc= 25 ć unless oth erwise specified


Symbol Parameter Maximum Units
VDSS Drain-to-Source Voltage (NOTE *1) 800 V
ID Continuous Drain Current 10
ID@ 100 ć Continuous Drain Current Figure3 A

IDM Pulsed Drain Current, VGS@ 10V (NOTE *2) Figure6


Power Dissipation 60 W
PD
W/ C
O

Derating Factor above 25ć


V GS Gate-to-Source Voltage f20 V
EAS Single Pulse Avalanche Engergy; 440 mJ
V ESD(GS) Gate Source ESD Voltage(HBM,c=100pF,R=1.5K¡ ) 6000 V
dv/dt Peak Diode Recovery dv/dt (NOTE *3) 5.0 V/ns
Maximum Temperature for Soldering
TL 300
Leads at 0.063in(1.6mm) from Case for 10 seconds ć
T PKG 260
Package Body for 10 seconds
T J and T STG Operation Junction and Storage Temperature Range 150, -55 to 150 ć
Caution: Stresses greater than those listed in “Absolute Maximum Ratings” Table may cause permanent damage to the device.
Thermal Resistance
Symbol Parameter Maximum Units Test Condition
Drain lead soldered to water cooled
R șJC Junction-to-Case 2.27
heatsink, PD ad-justed for a peak
ć /W
junction temperature of +150oC.
R șJA Junction-to-Ambient 100 1 cubic foot chamber, free air.

©2013 InPower Semiconductor Co., Ltd. Page 1 of 9 ISA10N80A Rev.A. Jul. 2013
Electrical Characteristics TJ= 25 ć unless otherwise specified ˖
OFF Characteristics
Rating
Symbol Parameter Units Test ConditionV
Min. Typ. Max.
V DSS Drain-to-Source BreakdowQ Voltage 800 -- -- V V GS =0V, I D =250μA
Reference to 25ć ,
ǻBV DSS /ǻT J Bvdss Temperature Coefficient -- 0.5 -- V/ć
ID=250uA
V DS = 800V, V GS =0V,
-- -- 1.0
T a = 25ć
I DS(off) Off-State Drain-to-Source Current uA
V DS =640V, V GS = 0 V,
-- -- 100
T a = 125ć
I GSS(F) Gate-to-Source Forward Leakage -- -- 1.0 V GS =+20V
uA
I GSS(R) Gate-to-Source Reverse Leakage -- -- -1.0 V GS =-20V

ON Characteristics
Rating
Symbol Parameter Units Test Conditions
Min. Typ. Max.
V GS =10V,I D =4.5A
R DS(ON) Drain-to-Source On-Resistance -- 0.80 0.90 Ÿ
(NOTE*4)
|V DS |>2I D *R DS (on) max
g fs Forward Transconductance -- 20 -- S I D =10A
(NOTE*4)
V GS(TH) Gate Threshold Voltage 2.0 -- 4.0 V V DS = V GS , I D = 250μA

Dynamic Characteristics
Rating
Symbol Parameter Units Test Conditions
Min. Typ. Max.
C iss Input Capacitance -- 2900 -- V GS =0V
V DS = 25V
C oss Output Capacitance -- 200 -- pF
f = 1.0MHz
C rss Reverse Transfer Capacitance -- 25 --

Qg Total Gate Charge -- 65 -- V DD =640V


I D =9.0A
Q gs Gate-to-Source Charge -- 13 -- nC
Vgs=10V
Q gd Gate-to-Drain (“Miller”)Charge -- 25 --

Resistive Switching Characteristics


Rating
Symbol Parameter Units Test Conditions
Min. Typ. Max.
t d(ON) Turn-on Delay Time -- 19 --
V DD = 400V
trise Rise Time -- 10 -- I D =9.0A
ns
V GS = 10V
t d(OFF) Turn-Off Delay Time -- 68 --
R G =4.7Ÿ
t fall Fall Time -- 23 --

©2013 InPower Semiconductor Co., Ltd. Page 2 of 9 ISA10N80A Rev.A. Jul. 2013
Source-Drain Diode Characteristics
Rating
Symbol Parameter Units Test Conditions
Min. Typ. Max.
IS Continuous Source Current (Body Diode) -- -- 10 A
Integral pn-diode in
MOSFET
I SM Maximum Pulsed Current (Body Diode) -- -- 40 A

V SD Diode Forward Voltage -- -- 1.5 V I S =10A,V GS =0V

trr Reverse Recovery Time -- 200 -- nS I F =10A,


T j = 25°C
Qrr Reverse Recovery Charge -- 2.2 -- uC di/dt=100A/us

Notes:

*1. TJ=+25ć to +150ć.


*2. Repetitive rating; pulse width limited by maximum junction temperature.
*3. ISD=10A di/dt”100A/us, VDD”BVDSS, TJmax=+150ć.
*4. Pulse width”380us; duty cycle”2%.

©2013 InPower Semiconductor Co., Ltd. Page 3 of 9 ISA10N80A Rev.A. Jul. 2013
&KDUDFWHULVWLFV&XUYH˖
Figure 1. Maximum Effective Thermal Impedance, Junction-to-Case
 Duty Factor
1.000
 50%
 20%
ZTJC, Thermal Impedance

10%
 5%
0.100 P
(Normalized)

DM

 2% t
t
1
2


0.010
1%
NOTES:
single pulse DUTY FACTOR: D=t1/t2
 PEAK TJ=PDM x ZTJC x RTJC+TC


0.001

1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
 tp, Rectangular Pulse Duration (s)


Figure 2. Maximum Power Dissipation Figure 3. Maximum Continuous Drain Current
 vs Case Temperature vs Case Temperature
100 12.5

80
PD, Power Dissipation (W)

10.0
ID, Drain Current (A)

60
7.5

40
 5.0

20
2.5

0
 0
25 50 75 100 125 150 25 50 75 100 125 150
 o
TC, Case Temperature ( C) TC, Case Temperature ( C) o



Figure 4. Typical Output Characteristics Figure5. Typical Drain-to-Source ON Resistance
 vs Gate Voltage and Drain Current
40 PULSE DURATION = 250 μS 2.8
PULSE DURATION = 250 μS
V
= 15
35 T = 25 C
DUTY FACTOR = 0.5% MAX GS
V
= 6.0 V
DUTY FACTOR = 0.5% MAX
RDS(ON), Drain-to-Source

o o
C VGS T = 25 C
C

30
ID, Drain Current (A)

ON Resistance (:

V = 5.75V
GS 2.1
ID = 20A
25 V = 5.5V
GS ID = 10A
20 1.4 ID = 4.5A
 V = 5.25V
GS

15 V = 5V
GS
10
0.7
5 V = 4.5V
GS

0 0
0 8 16 24 32 40 48 4 5 6 7 8 9 10 11 12 13 14 15

VDS, Drain-to-Source Voltage (V) V2GS, Gate-to-Source Voltage (V)

©2013 InPower Semiconductor Co., Ltd. Page 4 of 9 ISA10N80A Rev.A. Jul. 2013
Figure 6. Maximum Peak Current Capability

1000
TRANSCONDUCTANCE  FOR TEMPERATURES
ABOVE 25 oC DERATE PEAK
MAY LIMIT CURRENT IN
CURRENT AS FOLLOWS:
THIS REGION

IDM, Peak Current (A)

 – 7 &-
 100 , = ,  --------------------



 10

 VGS = 10V
1
 1E-6 10E-6 100E-6 1E-3 10E-3 100E-3 1E+0 10E+0
 tp, Pulse Width (s)

 Figure 7. Typical Transfer Characteristics Figure 8. Unclamped Inductive
 Switching Capability

 30
PULSE DURATION = 250 μs
100.0
ID, Drain-to-Source Current (A)

27 DUTY CYCLE = 0.5% MAX


 VDS = 10 V
IAS, Avalanche Current (A)

24

 21
10.0
18
 15 STARTING TJ = 25 oC

 12
STARTING TJ = 150 oC

1.0
9
 6
+150 oC
+25 oC If R= 0: tAV= (L×IAS)/(1.3BVDSS-VDD)

 3 -55 oC If Rz 0: tAV= (L/R) ln[IAS×R)/(1.3BVDSS-VDD)+1]


R equals total Series resistance of Drain circuit

 0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
0.1
1E-6 10E-6 100E-6 1E-3 10E-3 100E-3
 VGS, Gate-to-Source Voltage (V) tAV, Time in Avalanche (s)



Figure 9. Typical Drain-to-Source ON Figure 10. Typical Drain-to-Source ON Resistance
 Resistance vs Drain Current vs Junction Temperature
 2.4 2.6
2.2 PULSE DURATION = 2 μs 2.4
 DUTY CYCLE = 0.5% MAX
RDS(ON), Drain-to-Source
RDS(ON), Drain-to-Source

2.0 2.2
Resistance (Normalized)

TC=25°C
 1.8 2.0
ON Resistance (:)

1.6 1.8
 1.4
V = 10V
1.6
1.2 GS 1.4
 1.0 1.2
0.8 1.0
 0.6 0.8
 0.4 0.6
0.4
PULSE DURATION = 250 μs
DUTY CYCLE = 0.5% MAX
0.2 VGS = 10V, ID =4.5A
 0 0.2
0 5 10 15 20 25 -75 -50 -25 0 25 50 75 100 125 150
 ID, Drain Current (A) TJ, Junction Temperature (oC)


©2013 InPower Semiconductor Co., Ltd. Page 5 of 9 ISA10N80A Rev.A. Jul. 2013
Figure 11. Typical Breakdown Voltage vs Figure 12. Typical Threshold Voltage vs
 Junction Temperature Junction Temperature

1.15 1.2
Breakdown Voltage (Normalized)

VGS(TH), Threshold Voltage


1.1
BVDSS, Drain-to-Source

1.10


(Normalized)
1.0

1.05
0.9

1.00
0.8
 VGS = VDS
0.95
0.7 ID = 250 μA
 VGS = 0V
ID = 250 μA

0.90 0.6
-75 -50 -25 0.0 25 50 75 100 125 150 -75 -50 -25 0.0 25 50 75 100 125 150
 TJ, Junction Temperature ( C)o
TJ, Junction Temperature ( C) o



 Figure 13. Maximum Forward Bias Safe Figure 14. Typical Capacitance vs
Operating Area Drain-to-Source Voltage

100.0 10000
o

 TJ = MAX RATED, TC = 25 C
Single Pulse 10μs

 Ciss
C, Capacitance (pF)
ID, Drain Current (A)

10

10.0 s 1000

1.0
 ms

10
1.0 m
s 100
VGS = 0V, f = 1MHz Coss
DC Ciss = Cgs + Cgd
 OPERATION IN THIS AREA MAY
BE LIMITED BY R
DS(ON)
Coss # Cds + Cgd
Crss = Cgd Crss
0.1 10

 1 10 100 1000 0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V) VDS, Drain Voltage (V)




 Figure 15. Typical Gate Charge Figure 16. Typical Body Diode Transfer
 vs Gate-to-Source Voltage Characteristics
12 80

VGS, Gate-to-Source Voltage (V)

ISD, Reverse Drain Current (A)

70
10 60
150 oC
8 VDS = 640V 50
o
25 C
6 40
-55 oC
4 30

2 20

10
0 ID = 9A VGS = 0V
0
 0 20 40 60 80 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

QG , Total Gate Charge (nC)


 VSD, Source-to-Drain Voltage (V)

©2013 InPower Semiconductor Co., Ltd. Page 6 of 9 ISA10N80A Rev.A. Jul. 2013
Test Circuits and Waveforms

VDS
ID
ID
VDS VGS
Miller
Region
VGS
VDD
D.U.T.
VGS(TH)

1 mA
Qgs Qgd
Qg

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveform

VDS
RL 90%
VDS

VGS
VDD
RG D.U.T.
10%
VGS

td(ON) trise td(OFF) tfall

Figure 19. Resistive Switching Test Circuit Figure 20. Resistive Switching Waveforms

©2013 InPower Semiconductor Co., Ltd. Page 7 of 9 ISA10N80A Rev.A. Jul. 2013
Test Circuits and Waveforms

di/dt adj. Current


Pump

di/dt = 100A/μA
ID
Double Pulse

D.U.T. VDD
Qrr
L
trr

ID

Figure 22. Diode Reverse Recovery Waveform

Figure 21. Diode Reverse Recovery Test Circuit

BVDSS

Series Switch
(MOSFET)
L
IAS

BVDSS

D.U.T. VDD VDD


Commutating
Diode
0 tAV

VGS 50:
IAS
VGS tp

I AS 2 L
E AS
2

Figure 23. Unclamped Inductive Switching Test Circuit Figure 24. Unclamped Inductive Switching Waveforms

©2013 InPower Semiconductor Co., Ltd. Page 8 of 9 ISA10N80A Rev.A. Jul. 2013
Disclaimers:
InPower Semiconductor Co., Ltd (IPS) reserves the right to make changes without notice in order to improve reliability,
function or design and to discontinue any product or service without notice. Customers should obtain the latest relevant
information before orders and should verify that such information is current and complete. All products are sold subject to
IPS’s terms and conditions supplied at the time of order acknowledgement.

InPower Semiconductor Co., Ltd warrants performance of its hardware products to the specifications at the time of sale,
Testing, reliability and quality control are used to the extent IPS deems necessary to support this warrantee. Except where
agreed upon by contractual agreement, testing of all parameters of each product is not necessarily performed.

InPower Semiconductor Co., Ltd does not assume any liability arising from the use of any product or circuit designs
described herein. Customers are responsible for their products and applications using IPS’s components. To minimize risk,
customers must provide adequate design and operating safeguards.

InPower Semiconductor Co., Ltd does not warrant or convey any license either expressed or implied under its patent
rights, nor the rights of others. Reproduction of information in IPS’s data sheets or data books is permissible only if
reproduction is without modification or alteration. Reproduction of this information with any alteration is an unfair and
deceptive business practice. InPower Semiconductor Co., Ltd is not responsible or liable for such altered documentation.

Resale of IPS’s products with statements different from or beyond the parameters stated by InPower Semiconductor Co.,
Ltd for that product or service voids all express or implied warrantees for the associated IPS’s product or service and is
unfair and deceptive business practice. InPower Semiconductor Co., Ltd is not responsible or liable for any such
statements.
The MOSFET device is electrostatic sensitive. Proper electrostatic discharge (ESD) protection shall be implemented to
avoid damaging the device.

Life Support Policy:

InPower Semiconductor Co., Ltd’s products are not authorized for use as critical components in life support devices or
systems without the expressed written approval of InPower Semiconductor Co., Ltd.

As used herein:
1. Life support devices or systems are devices or systems which:
a. are intended for surgical implant into the human body,
b. support or sustain life,
c. whose failure to perform when properly used in accordance with instructions
for used provided in the labeling, can be reasonably expected to result in significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

©2013 InPower Semiconductor Co., Ltd. Page 9 of 9 ISA10N80A Rev.A. Jul. 2013

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