ITA09N50A

N-Channel MOSFET Pb Lead Free Package and Finish

Applications:
• Adaptor VDSS RDS(ON) (Typ.) ID
• Charger 500 V 0.55 : 9.0 A
• SMPS Standby Power
Features:
• RoHS Compliant D
• Low ON Resistance
• Low Gate Charge
• Peak Current vs Pulse Width Curve

G G
D
Ordering Information S

PART NUMBER PACKAGE BRAND TO-220F

S
ITA09N50A Not to Scale
ITA09N50A TO-220F

Absolute Maximum Ratings TC=25 oC unless otherwise specified

Symbol Parameter ITA09N50A Units
VDSS Drain-to-Source Voltage (NOTE *1) 500 V
ID Continuous Drain Current 9.0*
o
ID@ 100 C Continuous Drain Current Figure 3 A
IDM Pulsed Drain Current, VGS@ 10V (NOTE *2) Figure 6
Power Dissipation 50 W
PD o o
Derating Factor above 25 C 0.4
0.24 W/ C
VGS Gate-to-Source Voltage ± 20 V
Single Pulse Avalanche Engergy
EAS 630 mJ
L=10 mH
IAS Pulsed Avalanche Rating Figure 8 A

dv/dt Peak Diode Recovery dv/dt (NOTE *3) 5.0 V/ns

Maximum Temperature for Soldering
TL Leads at 0.063 in (1.6 mm) from Case for 10 seconds 300
TPKG Package Body for 10 seconds 260
o
C
Operating Junction and Storage
TJ and TSTG -55 to 150
Temperature Range
* Drain Current Limited by Maximum Junction Temperature
Caution: Stresses greater than those listed in the “Absolute Maximum Ratings” Table may cause permanent damage to the device

Thermal Resistance
Symbol Parameter ITA09N50A Units Test Conditions
Drain lead soldered to water cooled heatsink, PD ad-
RTJC Junction-to-Case 2.5 o
justed for a peak junction temperature of +150 C.
o
C/W
RTJA Junction-to-Ambient 100 1 cubic foot chamber, free air.

©2012 InPower Semiconductor Co., Ltd. Page 1 of 9 ITA09N50A REV.A. Mar. 2012
 o
OFF Characteristics TJ=25 C unless otherwise specified
Symbol Parameter Min. Typ. Max. Units Test Conditions
BVDSS Drain-to-Source Breakdown Voltage 500 -- -- V VGS=0V, ID=250μA
o
BreakdownVoltage Temperature Reference to 25 C,
'BVDSS /' TJ -- 0.6 -- V/ C
o
Coefficient, Figure 11. ID=250μA

-- -- 1.0 VDS=500V, VGS=0V

IDSS Drain-to-Source Leakage Current μA
VDS=400V, VGS=0V
-- -- 100 o
TJ=125 C
Gate-to-Source Forward Leakage -- -- 1.0 VGS=+20V
IGSS uA
Gate-to-Source Reverse Leakage -- -- -1.0 VGS= -20V

ON Characteristics TJ=25 oC unless otherwise specified

Symbol Parameter Min. Typ. Max. Units Test Conditions
Static Drain-to-Source On-Resistance VGS=10V, ID=5.0A
RDS(ON) -- 0.55 0.75 :
Figure 9 and 10. (NOTE *4)
VGS(TH) Gate Threshold Voltage, Figure 12. 2.0 -- 4.0 V VDS=VGS, ID=250PA
VDS=20V, ID=9.0A
gfs Forward Transconductance -- 11 -- S
(NOTE *4)

Dynamic Characteristics Essentially independent of operating temperature

Symbol Parameter Min. Typ. Max. Units Test Conditions
Ciss Input Capacitance -- 1253 -- VGS=0V
Coss Output Capacitance -- 130 -- VDS=25V
pF
f =1.0MHz
Crss Reverse Transfer Capacitance -- 18 --
Figure 14
Qg Total Gate Charge -- 28 -- VDD=250V
Qgs Gate-to-Source Charge -- 7 -- nC ID=9A
Qgd Gate-to-Drain (“Miller”) Charge -- 11 -- Figure 15

Resistive Switching Characteristics Essentially independent of operating temperature

Symbol Parameter Min. Typ. Max. Units Test Conditions
td(ON) Turn-on Delay Time -- 18 -- VDD=250V
trise Rise Time -- 32 -- ID=9A
ns
td(OFF) Turn-Off Delay Time -- 80 -- VGS=10V
tfall Fall Time -- 38 -- RG=25:

©2012 InPower Semiconductor Co., Ltd. Page 2 of 9 ITA09N50A REV.A. Mar. 2012
 o
Source-Drain Diode Characteristics Tc=25 C unless otherwise specified
Symbol Parameter Min. Typ. Max. Units Test Conditions
IS Continuous Source Current (Body Diode) -- -- 9.0 A Integral pn-diode
ISM Maximum Pulsed Current (Body Diode) -- -- 36 A in MOSFET
VSD Diode Forward Voltage -- -- 1.5 V IS=9A, VGS=0V
trr Reverse Recovery Time -- 330 -- ns VGS=0V
Qrr Reverse Recovery Charge -- 1550 -- nC IF=9A, di/dt=100 A/μs

Notes:

*1. TJ = +25 oC to +150 oC.

*2. Repetitive rating; pulse width limited by maximum junction temperature.
*3. ISD= 9A di/dt < 100 A/μs, VDD < BVDSS, TJ=+150 oC.
*4. Pulse width < 380μs; duty cycle < 2%.

©2012 InPower Semiconductor Co., Ltd. Page 3 of 9 ITA09N50A REV.A. Mar. 2012
 Duty Factor Figure 1. Maximum Effective Thermal Impedance, Junction-to-Case
1.000
50%
20%
ZTJC, Thermal Impedance

10%
0.100
5%
(Normalized)

2%
0.010 PDM
1%
t1
t2
0.001
NOTES:
single pulse DUTY FACTOR: D=t1/t2
PEAK TJ=PDM x ZTJC x RTJC+TC

0.0001
1E-6 10E-6 100E-6 1E-3 10E-3 100E-3 1E+0 10E+0

tp, Rectangular Pulse Duration (s)

Figure 2. Maximum Power Dissipation Figure 3. Maximum Continuous Drain Current

vs Case Temperature vs Case Temperature

60 10
PD, Power Dissipation (W)

50
8
ID, Drain Current (A)

40
6
30
4
20

2
10

0 0
25 50 75 100 125 150 25 50 75 100 125 150

TC, Case Temperature ( C) o TC, Case Temperature (oC)

Figure 4. Typical Output Characteristics Figure 5. Typical Drain-to-Source ON Resistance

vs Gate Voltage and Drain Current

24 3.6
PULSE DURATION = 250 μS V PULSE DURATION = 10 μS
DUTY FACTOR = 0.5% = 15 DUTY FACTOR = 0.5% MAX
VGS
RDS(ON), Drain-to-Source

MAX, TC = 25 oC TC = 25 oC
VGS = 7.0V
ID, Drain Current (A)

18
ON Resistance (:

2.4
VGS = 6.5V
ID = 18A
12 ID = 9A
VGS = 6.0V ID = 4.5A
1.2
ID =2.25A
6 VGS = 5.5V

VGS = 5.0V

0 0.0
0 5 10 15 20 25 30 4 6 8 10 12 14
VDS, Drain-to-Source Voltage (V) VGS, Gate-to-Source Voltage (V)

©2012 InPower Semiconductor Co., Ltd. Page 4 of 9 ITA09N50A REV.A. Mar. 2012
 Figure 6. Maximum Peak Current Capability

100
TRANSCONDUCTANCE FOR TEMPERATURES
MAY LIMIT CURRENT IN ABOVE 25 oC DERATE PEAK
THIS REGION CURRENT AS FOLLOWS:

, = ,   – 7 &-
--------------------
IDM, Peak Current (A)



10

VGS = 10V

1
10E-6 100E-6 1E-3 10E-3 100E-3 1E+0 10E+0

tp, Pulse Width (s)

Figure 7. Typical Transfer Characteristics Figure 8. Unclamped Inductive

Switching Capability
25 100
PULSE DURATION = 10 μs
ID, Drain-to-Source Current (A)

DUTY CYCLE = 0.5% MAX

IAS, Avalanche Current (A)

VDS = 30 V
20

10
STARTING TJ = 25 oC
15
STARTING TJ = 150 oC

10
+150 oC 1
+25 oC
5 -55 oC If R= 0: tAV= (L×IAS)/(1.3BVDSS-VDD)
If Rz 0: tAV= (L/R) ln[IAS×R)/(1.3BVDSS-VDD)+1]
R equals total Series resistance of Drain circuit
0 0.1
2 3 4 5 6 1E-6 10E-6 100E-6 1E-3 10E-3

VGS, Gate-to-Source Voltage (V) tAV, Time in Avalanche (s)

Figure 9. Typical Drain-to-Source ON Figure 10. Typical Drain-to-Source ON Resistance

Resistance vs Drain Current vs Junction Temperature
2.75
2.50
RDS(ON), Drain-to-Source
Resistance (Normalized)

2.25
2.00
1.75
1.50
1.25
1.00
0.75 PULSE DURATION = 10 μs
DUTY CYCLE = 0.5% MAX
0.50 VGS = 10V, ID =5A
0.25
-75 -50 -25 0 25 50 75 100 125 150

T J, Junction Temperature (oC)

©2012 InPower Semiconductor Co., Ltd. Page 5 of 9 ITA09N50A REV.A. Mar. 2012
 Figure 11. Typical Breakdown Voltage vs Figure 12. Typical Threshold Voltage vs
Junction Temperature Junction Temperature
1.15 1.2
Breakdown Voltage (Normalized)

VGS(TH), Threshold Voltage

1.1
BVDSS, Drain-to-Source

1.10
1.0

(Normalized)
1.05
0.9

0.8
1.00

0.7
0.95
VGS = 0V 0.6 VGS = VDS
ID = 250 μA ID = 250 μA
0.90 0.5
-75 -50 -25 0 25 50 75 100 125 150 -75 -50 -25 0 25 50 75 100 125 150

TJ, Junction Temperature (oC) TJ, Junction Temperature (oC)

Figure 13. Maximum Forward Bias Safe Figure 14. Typical Capacitance vs
Operating Area Drain-to-Source Voltage
100.0 10000

10μs
Ciss
ID, Drain Current (A)

C, Capacitance (pF)

10.0 1000
100μs

1ms
1.0 100

Coss
10ms
0.1 OPERATION IN THIS AREA VGS = 0V, f = 1MHz
MAY BE LIMITED BY R
10 Ciss = Cgs + Cgd
DS(ON) Crss
DC Coss # Cds + Cgd
TJ = MAX RATED
Crss = Cgd
0.01 TC = 25 oC
1
1 10 100 1000 0.1 1 10 100 1000

VDS, Drain-to-Source Voltage (V) VDS, Drain Voltage (V)

Figure 15. Typical Gate Charge Figure 16. Typical Body Diode Transfer
vs Gate-to-Source Voltage Characteristics
12
VGS, Gate-to-Source Voltage (V)

10
VDS = 125V
VDS = 250V
8
VDS = 375V

2
ID = 9.0A
0
0 10 20 30

QG , Total Gate Charge (nC)

©2012 InPower Semiconductor Co., Ltd. Page 6 of 9 ITA09N50A REV.A. Mar. 2012
 Test Circuits and Waveforms

VDS
ID
ID
VDS VGS
Miller
Region
VGS
VDD
D.U.T.
VGS(TH)

1 mA
Qgs Qgd
Qg

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveform

VDS
RL 90%
VDS

VGS
VDD
RG D.U.T.
10%
VGS

td(ON) trise td(OFF) tfall

Figure 19. Resistive Switching Test Circuit Figure 20. Resistive Switching Waveforms

©2012 InPower Semiconductor Co., Ltd. Page 7 of 9 ITA09N50A REV.A. Mar. 2012
 Test Circuits and Waveforms

di/dt adj. Current

Pump

di/dt = 100A/μA
ID
Double Pulse

D.U.T. VDD
Qrr
L
trr

ID

Figure 22. Diode Reverse Recovery Waveform

Figure 21. Diode Reverse Recovery Test Circuit

BVDSS

Series Switch
(MOSFET)
L
IAS

BVDSS

D.U.T. VDD VDD

Commutating
Diode
0 tAV

VGS 50:
IAS
VGS tp

I AS 2 L
E AS
2

Figure 23. Unclamped Inductive Switching Test Circuit Figure 24. Unclamped Inductive Switching Waveforms

©2012 InPower Semiconductor Co., Ltd. Page 8 of 9 ITA09N50A REV.A. Mar. 2012
 Disclaimers:
InPower Semiconductor Co., Ltd (IPS) reserves the right to make changes without notice in order to improve reliability, function
or design and to discontinue any product or service without notice. Customers should obtain the latest relevant information before
orders and should verify that such information is current and complete. All products are sold subject to IPS’s terms and conditions
supplied at the time of order acknowledgement.

InPower Semiconductor Co., Ltd warrants performance of its hardware products to the specifications at the time of sale, Testing,
reliability and quality control are used to the extent IPS deems necessary to support this warrantee. Except where agreed upon
by contractual agreement, testing of all parameters of each product is not necessarily performed.

InPower Semiconductor Co., Ltd does not assume any liability arising from the use of any product or circuit designs described
herein. Customers are responsible for their products and applications using IPS’s components. To minimize risk, customers must
provide adequate design and operating safeguards.

InPower Semiconductor Co., Ltd does not warrant or convey any license either expressed or implied under its patent rights, nor
the rights of others. Reproduction of information in IPS’s data sheets or data books is permissible only if reproduction is without
modification or alteration. Reproduction of this information with any alteration is an unfair and deceptive business practice.
InPower Semiconductor Co., Ltd is not responsible or liable for such altered documentation.

Resale of IPS’s products with statements different from or beyond the parameters stated by InPower Semiconductor Co., Ltd
for that product or service voids all express or implied warrantees for the associated IPS’s product or service and is unfair and
deceptive business practice. InPower Semiconductor Co., Ltd is not responsible or liable for any such statements.

Life Support Policy:

InPower Semiconductor Co., Ltd’s products are not authorized for use as critical components in life support devices or
systems without the expressed written approval of InPower Semiconductor Co., Ltd.

As used herein:
1. Life support devices or systems are devices or systems which:
a. are intended for surgical implant into the human body,
b. support or sustain life,
c. whose failure to perform when properly used in accordance with instructions
for used provided in the labeling, can be reasonably expected to result in significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.


©2012 InPower Semiconductor Co., Ltd. Page 9 of 9 ITA09N50A REV.A. Mar. 2012