IRLI530NPbF
 Logic –Level Gate Drive HEXFET® Power MOSFET
 Advanced Process Technology
 Isolated Package   VDSS 100V
 High Voltage Isolation = 2.5KVRMS 
 Sink to Lead Creepage Dist. = 4.8mm RDS(on) 0.10
 Fully Avalanche Rated
ID 12A
 Lead-Free

Description
Fifth Generation HEXFETs from International Rectifier utilize
advanced processing techniques to achieve extremely low on-
resistance per silicon area. This benefit, combined with the fast S
D
switching speed and ruggedized device design that HEXFET G
Power MOSFETs are well known for, provides the designer with
an extremely efficient and reliable device for use in a wide variety TO-220 Full-Pak
of applications.
G D S
The TO-220 Fullpak eliminates the need for additional insulating Gate Drain Source
hardware in commercial-industrial applications. The moulding
compound used provides a high isolation capability and a low
thermal resistance between the tab and external heatsink. This
isolation is equivalent to using a 100 micron mica barrier with
standard TO-220 product. The Fullpak is mounted to a heatsink
using a single clip or by a single screw fixing.

Standard Pack
Base Part Number Package Type Orderable Part Number
Form Quantity
IRLI530NPbF TO-220 Full-Pak Tube 50 IRLI530NPbF

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 12
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 8.6 A
IDM Pulsed Drain Current  60
PD @TC = 25°C Maximum Power Dissipation 41 W
Linear Derating Factor 0.27 W/°C
VGS Gate-to-Source Voltage ± 16 V
EAS Single Pulse Avalanche Energy (Thermally Limited)  150 mJ
IAR Avalanche Current  9.0 A
EAR Repetitive Avalanche Energy  4.1 mJ
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
TJ Operating Junction and -55 to + 175  
TSTG Storage Temperature Range °C 
Soldering Temperature, for 10 seconds (1.6mm from case) 300  
Mounting torque, 6-32 or M3 screw 10 lbf•in (1.1N•m)  

Thermal Resistance  
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case ––– 3.7
°C/W
RJA Junction-to-Ambient ––– 65

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Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.122 ––– V/°C Reference to 25°C, ID = 1mA 
––– ––– 0.100 VGS = 10V, ID = 9.0A
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.120  VGS = 5.0V, ID = 9.0A
––– ––– 0.150 VGS = 4.0V, ID = 8.0A
VGS(th) Gate Threshold Voltage 1.0 ––– 2.0 V VDS = VGS, ID = 250µA
gfs Forward Trans conductance 7.7 ––– ––– S VDS = 50V, ID = 9.0A
––– ––– 25 VDS = 100V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 80V,VGS = 0V,TJ =150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 16V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
Qg Total Gate Charge ––– ––– 34 ID = 9.0A
Qgs Gate-to-Source Charge ––– ––– 4.8 nC   VDS = 80V
Qgd Gate-to-Drain Charge ––– ––– 20 VGS = 5.0V , See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 7.2 ––– VDD = 50V
tr Rise Time ––– 53 ––– ID = 9.0A
ns
td(off) Turn-Off Delay Time ––– 30 ––– RG= 6.0VGS = 5.0V 
tf Fall Time ––– 26 ––– RD= 5.5See Fig. 10
Between lead,
LD Internal Drain Inductance ––– 4.5 –––
6mm (0.25in.)
nH  
from package
LS Internal Source Inductance ––– 7.5 –––
and center of die contact
Ciss Input Capacitance ––– 800 ––– VGS = 0V
Coss Output Capacitance ––– 160 ––– VDS = 25V
pF  
Crss Reverse Transfer Capacitance ––– 90 ––– ƒ = 1.0MHz, See Fig. 5
C Drain to Sink Capacitance ––– 12 ––– ƒ = 1.0MHz
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
Continuous Source Current MOSFET symbol
IS ––– ––– 12
(Body Diode) showing the
A
Pulsed Source Current integral reverse
ISM ––– ––– 60
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C,IS = 6.6A,VGS = 0V 
trr Reverse Recovery Time ––– 140 210 ns TJ = 25°C ,IF = 9.0A
Qrr Reverse Recovery Charge ––– 740 1100 nC di/dt = 100A/µs 
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)
 Starting TJ = 25°C, L = 3.1mH, RG = 25, IAS = 9.0A (See fig. 12)
 ISD 9.0A, di/dt 540A/µs, VDD V(BR)DSS, TJ  175°C.
 Pulse width 300µs; duty cycle  2%.
 t=60s, ƒ=60Hz
 Uses IRL530N data and test conditions.

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100 100
VGS VGS
TOP 15V TOP 15V
12V 12V
10V 10V
8.0V 8.0V
ID , Drain-to-Source Current (A)

ID , Drain-to-Source Current (A)

6.0V 6.0V
4.0V 4.0V
3.0V 3.0V
BOTTOM 2.5V BOTTOM 2.5V
10 10

2.5V
1 1

2.5V

20µs PULSE WIDTH 20µs PULSE WIDTH

T J = 25°C T J = 175°C
0.1 A 0.1 A
0.1 1 10 100 0.1 1 10 100
VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig. 1 Typical Output Characteristics Fig. 2 Typical Output Characteristics

100 3.0
I D = 15A
R DS(on) , Drain-to-Source On Resistance

TJ = 25°C
I D , Drain-to-Source Current (A)

2.5
TJ = 175°C

10 2.0
(Normalized)

1.5

1 1.0

0.5

V DS = 50V
20µs PULSE WIDTH VGS = 10V
0.1 0.0 A
A
2 3 4 5 6 7 8 9 10 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature (°C)

Fig. 3 Typical Transfer Characteristics Fig. 4 Normalized On-Resistance

vs. Temperature

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IRLI530NPbF

1400 15
V GS = 0V, f = 1MHz I D = 9.0A
C iss = Cgs + C gd , Cds SHORTED V DS = 80V

V GS , Gate-to-Source Voltage (V)

1200 C rss = C gd V DS = 50V
C oss = C ds + C gd 12 V DS = 20V
1000
Ciss
C, Capacitance (pF)

9
800

600 6
Coss
400
Crss 3
200
FOR TEST CIRCUIT
SEE FIGURE 13
0 0 A
A
1 10 100 0 10 20 30 40 50

VDS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Fig 6. Typical Gate Charge vs.

Drain-to-Source Voltage Gate-to-Source Voltage

100
1000
OPERATION IN THIS AREA LIMITED
BY R DS(on)
ISD , Reverse Drain Current (A)

I D , Drain Current (A)

TJ = 175°C 100

10µs
10
TJ = 25°C

10 100µs

TC = 25°C 1ms
TJ = 175°C
VGS = 0V Single Pulse 10ms
1 A 1 A
0.4 0.6 0.8 1.0 1.2 1.4 1 10 100 1000
VDS , Drain-to-Source Voltage (V)
VSD , Source-to-Drain Voltage (V)

Fig. 7 Typical Source-to-Drain Diode

Fig 8. Maximum Safe Operating Area
Forward Voltage

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IRLI530NPbF

12

9
ID , Drain Current (A)

Fig 10a. Switching Time Test Circuit

0
25 50 75 100 125 150 175
TC , Case Temperature ( °C)

Fig 9. Maximum Drain Current vs. Case Temperature

Fig 10b. Switching Time Waveforms

10
Thermal Response (Z thJC)

D = 0.50

1
0.20

0.10

0.05
PDM
0.02
0.1 0.01 SINGLE PULSE t1
(THERMAL RESPONSE)
t2

Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x ZthJC + TC
0.01
0.00001 0.0001 0.001 0.01 0.1 1
t1, Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRLI530NPbF

350
ID

EAS , Single Pulse Avalanche Energy (mJ)

TOP 3.7A
300 6.4A
BOTTOM 9.0A
15V
250

L DRIVER 200
VDS

150
RG D.U.T +
V
- DD
IAS A
20V 100
tp 0.01

50
Fig 12a. Unclamped Inductive Test Circuit
VDD = 25V
0 A
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
V(BR)DSS
tp Fig 12c. Maximum Avalanche Energy
vs. Drain Current

I AS

Fig 12b. Unclamped Inductive Waveforms

Fig 13a. Gate Charge Waveform Fig 13b. Gate Charge Test Circuit

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IRLI530NPbF

Fig 14. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs

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IRLI530NPbF

TO-220 Full-Pak Package Outline (Dimensions are shown in millimeters (inches))

TO-220 Full-Pak Part Marking Information

TO-220AB Full-Pak packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to website at http://www.irf.com/package/

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IRLI530NPbF
Qualification Information 
Industrial
Qualification Level  
(per JEDEC JESD47F) †
Moisture Sensitivity Level   TO-220 Full-Pak N/A
RoHS Compliant Yes

† Applicable version of JEDEC standard at the time of product release.

Revision History

Date Comments
 Changed datasheet with Infineon logo - all pages.
04/27/2017  Corrected Package Outline on page 8.
 Added disclaimer on last page.

Trademarks of Infineon Technologies AG

µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™,
CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™,
GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™,
OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID
FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™

Trademarks updated November 2015

Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.

Edition 2016-04-19
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
Email: erratum@infineon.com
Document reference
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IMPORTANT NOTICE
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event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
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In addition, any information given in this
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customer’s applications.
The data contained in this document is exclusively
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departments to evaluate the suitability of the
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completeness of the product information given in
this document with respect to such application.
For further information on the product, technology,
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
Please note that this product is not qualified
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Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
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Except as otherwise explicitly approved by Infineon
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