IRLIZ34NPbF

 Logic –Level Gate Drive HEXFET® Power MOSFET

 Advanced Process Technology
 Isolated Package VDSS 55V
 High Voltage Isolation = 2.5KVRMS 
 Sink to Lead Creepage Dist. = 4.8mm RDS(on) 0.035
 Fully Avalanche Rated
ID 22A
 Lead-Free

Description
Fifth Generation HEXFETs from International Rectifier utilize
advanced processing techniques to achieve extremely low on-
resistance per silicon area. This benefit, combined with the fast S
D
switching speed and ruggedized device design that HEXFET G
Power MOSFETs are well known for, provides the designer with
an extremely efficient and reliable device for use in a wide variety TO-220 Full-Pak
of applications.
G D S
The TO-220 Full Pak eliminates the need for additional insulating Gate Drain Source
hardware in commercial-industrial applications. The molding
compound used provides a high isolation capability and a low
thermal resistance between the tab and external heat sink. This
isolation is equivalent to using a 100 micron mica barrier with
standard TO-220 product. The Fullpak is mounted to a heat sink
using a single clip or by a single screw fixing.

Standard Pack
Base Part Number Package Type Orderable Part Number
Form Quantity
IRLIZ34NPbF TO-220 Full-Pak Tube 50 IRLIZ34NPbF

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 22
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 15 A
IDM Pulsed Drain Current  110
PD @TC = 25°C Maximum Power Dissipation 37 W
Linear Derating Factor 0.24 W/°C
VGS Gate-to-Source Voltage ± 16 V
EAS Single Pulse Avalanche Energy (Thermally Limited)  110 mJ
IAR Avalanche Current  16 A
EAR Repetitive Avalanche Energy  3.7 mJ
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds (1.6mm from case) 300
Mounting torque, 6-32 or M3 screw 10 lbf•in (1.1N•m)

Thermal Resistance
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case ––– 4.1
°C/W
RJA Junction-to-Ambient ––– 65

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Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V VGS = 0V, ID = 250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– 0.065 ––– V/°C Reference to 25°C, ID = 1mA 
––– ––– 0.035 VGS = 10V, ID = 12A
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.046  VGS = 5.0V, ID = 12A
––– ––– 0.060 VGS = 4.0V, ID = 10A
VGS(th) Gate Threshold Voltage 1.0 ––– 2.0 V VDS = VGS, ID = 250µA
gfs Forward Trans conductance 11 ––– ––– S VDS = 25V, ID = 16A
––– ––– 25 VDS = 55V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 44V,VGS = 0V,TJ =150°C
Gate-to-Source Forward Leakage ––– ––– 100 VGS = 16V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -16V
Qg Total Gate Charge ––– ––– 25 ID = 16A
Qgs Gate-to-Source Charge ––– ––– 5.2 nC VDS = 44V
Qgd Gate-to-Drain Charge ––– ––– 14 VGS = 5.0V , See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 8.9 ––– VDD = 28V
tr Rise Time ––– 100 ––– ID = 16A
ns
td(off) Turn-Off Delay Time ––– 29 ––– RG= 6.5VGS = 5.0V 
tf Fall Time ––– 21 ––– RD= 1.8See Fig. 10
Between lead,
LD Internal Drain Inductance ––– 4.5 –––
6mm (0.25in.)
nH
from package
LS Internal Source Inductance ––– 7.5 –––
and center of die contact
Ciss Input Capacitance ––– 880 ––– VGS = 0V
Coss Output Capacitance ––– 220 ––– VDS = 25V
pF
Crss Reverse Transfer Capacitance ––– 94 ––– ƒ = 1.0MHz, See Fig. 5
C Drain to Sink Capacitance ––– 12 ––– ƒ = 1.0MHz
Source-Drain Ratings and Characteristics
Parameter Min. Typ. Max. Units Conditions
Continuous Source Current MOSFET symbol
IS ––– ––– 22
(Body Diode) showing the
A
Pulsed Source Current integral reverse
ISM ––– ––– 110
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C,IS = 12A,VGS = 0V 
trr Reverse Recovery Time ––– 76 110 ns TJ = 25°C ,IF = 16A
Qrr Reverse Recovery Charge ––– 190 290 nC di/dt = 100A/µs 

Notes:
 Repetitive rating; pulse width limited by max. junction temperature. (See fig. 11)
 VDD =25V, Starting TJ = 25°C, L = 610H, RG = 25, IAS = 16A (See fig. 12)
 ISD 16A, di/dt 270A/µs, VDD V(BR)DSS, TJ  175°C.
 Pulse width 300µs; duty cycle  2%.
 t=60s, ƒ=60Hz
 Uses IRLZ34N data and test conditions.

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10000 10000
VGS VGS
TOP 15V TOP 7.50V
12V 5.00V
10V 4.00V
1000 8.0V 1000 3.50V
I D , Drain-to-Source Current (A)

6.0V

ID , Drain-to-Source Current (A)

3.00V
4.0V 2.75V
3.0V 2.50V
100 BOTTOM 2.0V BOTTOM 2.25V
100

10 10

1 1
2.0V
0.1 0.1

0.01
2.0V
0.01
20µs PULSE WIDTH 20µs PULSE WIDTH
TJ = 25°C A TJ = 175°C
0.001 0.001 A
0.1 1 10 100 0.1 1 10 100
VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V)
Fig. 1 Typical Output Characteristics Fig. 2 Typical Output Characteristics

1000 3.0
I D = 27A
R DS(on) , Drain-to-Source On Resistance

TJ = 25°C
I D , Drain-to-Source Current (A)

2.5
100

TJ = 175°C
2.0
(Normalized)

10

1.5

1
1.0

0.1
0.5

V DS = 25V
20µs PULSE WIDTH VGS = 10V
0.01 0.0 A
A -60 -40 -20 0 20 40 60 80 100 120 140 160 180
2 3 4 5 6 7 8 9 10

VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature (°C)

Fig. 3 Typical Transfer Characteristics Fig. 4 Normalized On-Resistance

vs. Temperature

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1400 15
V GS = 0V, f = 1MHz I D = 16A
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd

VGS , Gate-to-Source Voltage (V)

1200 V DS = 44V
Ciss C oss = Cds + C gd 12 V DS = 28V
1000
C, Capacitance (pF)

9
800

Coss
600
6

400
Crss 3
200
FOR TEST CIRCUIT
SEE FIGURE 13
0 A 0 A
1 10 100 0 4 8 12 16 20 24 28 32
VDS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Fig 6. Typical Gate Charge vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000 1000
OPERATION IN THIS AREA LIMITED
BY R DS(on)
ISD , Reverse Drain Current (A)

I D , Drain Current (A)

100 100

10µs

TJ = 175°C

TJ = 25°C 100µs

10 10

1ms

TC = 25°C
TJ = 175°C
10ms
VGS = 0V Single Pulse
1 A 1 A
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1 10 100

VSD , Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig. 7 Typical Source-to-Drain Diode

Fig 8. Maximum Safe Operating Area
Forward Voltage

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25

20
ID , Drain Current (A)

15

10
Fig 10a. Switching Time Test Circuit

0
25 50 75 100 125 150 175
TC , Case Temperature ( °C)

Fig 9. Maximum Drain Current vs. Case Temperature

Fig 10b. Switching Time Waveforms

10
Thermal Response (Z thJC)

D = 0.50

1 0.20

0.10

0.05

0.02 PDM
0.1 0.01 SINGLE PULSE
(THERMAL RESPONSE) t1
t2

Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x ZthJC + TC
0.01
0.00001 0.0001 0.001 0.01 0.1 1
t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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250
ID

EAS , Single Pulse Avalanche Energy (mJ)

TOP 6.6A
11A
200 BOTTOM 16A

15V

150

L DRIVER
VDS

100
RG D.U.T +
V
- DD
IAS A
20V
tp 0.01 50

Fig 12a. Unclamped Inductive Test Circuit VDD = 25V

0 A
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
V(BR)DSS
tp Fig 12c. Maximum Avalanche Energy
vs. Drain Current

I AS

Fig 12b. Unclamped Inductive Waveforms

Fig 13a. Gate Charge Waveform Fig 13b. Gate Charge Test Circuit

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Fig 14. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs

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TO-220 Full-Pak Package Outline (Dimensions are shown in millimeters (inches))

TO-220 Full-Pak Part Marking Information

TO-220AB Full-Pak packages are not recommended for Surface Mount Application.

Note: For the most current drawing please refer to website at http://www.irf.com/package/

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Qualification Information
Industrial
Qualification Level
(per JEDEC JESD47F) †
Moisture Sensitivity Level TO-220 Full-Pak N/A
RoHS Compliant Yes

† Applicable version of JEDEC standard at the time of product release.

Revision History

Date Comments
 Changed datasheet with Infineon logo - all pages.
04/27/2017  Corrected Package Outline on page 8.
 Added disclaimer on last page.

Trademarks of Infineon Technologies AG

µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™,
CoolSiC™, DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™,
GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™,
OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID
FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™

Trademarks updated November 2015

Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.

Edition 2016-04-19
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2016 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
Email: erratum@infineon.com
Document reference
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