PD - 95511B

IRFR3505PbF
IRFU3505PbF
Features HEXFET® Power MOSFET
l Advanced Process Technology
D
l Ultra Low On-Resistance
l 175°C Operating Temperature
VDSS = 55V
l Fast Switching
l Repetitive Avalanche Allowed up to Tjmax RDS(on) = 0.013Ω
l Lead-Free G

ID = 30A
S
Description
This HEXFET® Power MOSFET utilizes the latest processing
techniques to achieve extremely low on-resistance per
silicon area. Additional features of this product are a 175°C
junction operating temperature, fast switching speed and
improved repetitive avalanche rating. These features
combine to make this design an extremely efficient and
reliable device for use in a wide variety of applications.
The D-Pak is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight D-Pak I-Pak
lead version (IRFU series) is for through-hole mounting IRFR3505PbF IRFU3505PbF
applications. Power dissipation levels up to 1.5 watts are
possible in typical surface mount applications.

Absolute Maximum Ratings

Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon limited) 71
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (See Fig.9) 49 A
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package limited) 30
IDM Pulsed Drain Current  280
PD @TC = 25°C Power Dissipation 140 W
Linear Derating Factor 0.92 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy‚ 210 mJ
EAS (tested) Single Pulse Avalanche Energy Tested Value‡ 410
IAR Avalanche Current See Fig.12a, 12b, 15, 16 A
EAR Repetitive Avalanche Energy† mJ
dv/dt Peak Diode Recovery dv/dt ƒ 4.0 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.09
RθJA Junction-to-Ambient (PCB mount)ˆ ––– 40 °C/W
RθJA Junction-to-Ambient ––– 110
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IRFR/U3505PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 55 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.057 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 0.011 0.013 Ω VGS = 10V, ID = 30A „
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250µA
gfs Forward Transconductance 41 ––– ––– S VDS = 25V, ID = 30A
––– ––– 20 VDS = 55V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 55V, VGS = 0V, TJ = 125°C
Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
Qg Total Gate Charge ––– 62 93 ID = 30A
Qgs Gate-to-Source Charge ––– 17 26 nC VDS = 44V
Qgd Gate-to-Drain ("Miller") Charge ––– 22 33 VGS = 10V„
td(on) Turn-On Delay Time ––– 13 ––– VDD = 28V
tr Rise Time ––– 74 ––– ID = 30A
ns
td(off) Turn-Off Delay Time ––– 43 ––– RG = 6.8Ω
tf Fall Time ––– 54 ––– VGS = 10V „
Between lead, D
LD Internal Drain Inductance ––– 4.5 –––
6mm (0.25in.)
nH
from package G

LS Internal Source Inductance ––– 7.5 –––

and center of die contact S

Ciss Input Capacitance ––– 2030 ––– VGS = 0V

Coss Output Capacitance ––– 470 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 91 ––– ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 2600 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 330 ––– VGS = 0V, VDS = 44V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance … ––– 630 ––– VGS = 0V, VDS = 0V to 44V

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current MOSFET symbol D

––– ––– 71
(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

––– ––– 280

(Body Diode)  p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 30A, VGS = 0V „
trr Reverse Recovery Time ––– 70 105 ns TJ = 25°C, IF = 30A, VDD = 28V
Qrr Reverse RecoveryCharge ––– 180 270 nC di/dt = 100A/µs „
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes  through ˆ are on page 11

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 IRFR/U3505PbF

1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

7.0V 7.0V
6.0V 6.0V
5.5V 5.5V
100 100 5.0V
5.0V
BOTTOM 4.5V BOTTOM 4.5V

4.5V
10 10

4.5V

20µs PULSE WIDTH 20µs PULSE WIDTH

Tj = 25°C Tj = 175°C
1 1
0.1 1 10 100 0.1 1 10 100

VDS, Drain-to-Source Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 70

T J = 25°C 60 T J = 25°C
G fs , Forward Transconductance (S)
ID, Drain-to-Source Current (Α)

T J = 175°C 50
100

40

30 T J = 175°C

10
20

VDS = 25V 10 VDS = 25V

20µs PULSE WIDTH 20µs PULSE WIDTH
1 0
4.0 5.0 6.0 7.0 8.0 9.0 10.0 0 10 20 30 40 50 60 70 80 90
VGS , Gate-to-Source Voltage (V) ID,Drain-to-Source Current (A)

Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance

Vs. Drain Current
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 IRFR/U3505PbF

4000 20
VGS = 0V, f = 1 MHZ
ID= 30A
Ciss = Cgs + Cgd, Cds SHORTED

VGS , Gate-to-Source Voltage (V)

Crss = Cgd VDS= 44V
16
3000 Coss = Cds + Cgd VDS= 28V
VDS= 11V
C, Capacitance (pF)

12
Ciss
2000
8

1000 Coss
4

Crss
0
0
0 20 40 60 80 100
1 10 100
Q G Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000.0 1000
OPERATION IN THIS AREA
LIMITED BY RDS(on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)

100.0
100
T J = 175°C

10.0 100µsec

10
1msec
1.0 T J = 25°C
Tc = 25°C
VGS = 0V Tj = 175°C
10msec
Single Pulse
0.1 1
0.0 0.5 1.0 1.5 2.0 2.5 1 10 100 1000
VSD, Source-toDrain Voltage (V) VDS , Drain-toSource Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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 IRFR/U3505PbF

80 2.5
LIMITED BY PACKAGE ID = 30A

RDS(on) , Drain-to-Source On Resistance

VGS = 10V

60 2.0
ID , Drain Current (A)

(Normalized)
40 1.5

20
1.0

0
0.5
25 50 75 100 125 150 175
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
T C , Case Temperature (°C)
T J , Junction Temperature (°C)

Fig 9. Maximum Drain Current Vs. Fig 10. Normalized On-Resistance

Case Temperature Vs. Temperature

10
Thermal Response ( Z thJC )

1
D = 0.50

0.20
0.1 0.10
0.05
0.02
0.01
0.01

SINGLE PULSE
( THERMAL RESPONSE )

0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRFR/U3505PbF

400
15V ID

EAS, Single Pulse Avalanche Energy (mJ)

TOP 12A
21A
BOTTOM 30A
L DRIVER 300
VDS

RG D.U.T +
V
- DD
IAS A 200
20V
VGS
tp 0.01Ω

Fig 12a. Unclamped Inductive Test Circuit 100

V(BR)DSS
tp

0
25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

I AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
QG

10 V
QGS QGD 4.0
VGS(th) Gate threshold Voltage (V)

VG 3.6

3.2
Charge ID = 250µA
Fig 13a. Basic Gate Charge Waveform 2.8
Current Regulator
Same Type as D.U.T.
2.4
50KΩ

12V .2µF
.3µF 2.0
+
V
D.U.T. - DS
1.6
VGS -75 -50 -25 0 25 50 75 100 125 150 175 200
3mA T J , Temperature ( °C )

IG ID
Current Sampling Resistors

Fig 13b. Gate Charge Test Circuit Fig 14. Threshold Voltage Vs. Temperature
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1000
Duty Cycle = Single Pulse

100 Allowed avalanche Current vs

Avalanche Current (A)

0.01 avalanche pulsewidth, tav

assuming ∆ Tj = 25°C due to
avalanche losses. Note: In no
0.05 case should Tj be allowed to
10
0.10 exceed Tjmax

0.1
1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

240 Notes on Repetitive Avalanche Curves , Figures 15, 16:

T OP Single Pulse (For further info, see AN-1005 at www.irf.com)
BOTT OM 10% Duty Cycle 1. Avalanche failures assumption:
200 ID = 30A Purely a thermal phenomenon and failure occurs at a
EAR , Avalanche Energy (mJ)

temperature far in excess of T jmax. This is validated for

every part type.
160 2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
120
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
80 avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
40 6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
0 tav = Average time in avalanche.
25 50 75 100 125 150 175 D = Duty cycle in avalanche = tav ·f
Starting TJ , Junction Temperature (°C) ZthJC(D, tav ) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Fig 16. Maximum Avalanche Energy Iav = 2DT/ [1.3·BV·Zth]
Vs. Temperature EAS (AR) = PD (ave)·tav
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IRFR/U3505PbF

Driver Gate Drive

P.W.
D.U.T P.W.
Period D=
Period
+

ƒ
*
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance
D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

RD
VDS

VGS
D.U.T.
RG
+
-VDD

10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %

Fig 18a. Switching Time Test Circuit

VDS
90%

10%
VGS
td(on) tr t d(off) tf

Fig 18b. Switching Time Waveforms

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 IRFR/U3505PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

EXAMPLE: THIS IS AN IRFR120
PART NUMBER
WITH AS SEMBLY INTERNATIONAL
LOT CODE 1234 RECTIFIER IRFR120 DATE CODE
AS SEMBLED ON WW 16, 2001 LOGO 116A YEAR 1 = 2001
IN THE ASS EMBLY LINE "A" 12 34 WEEK 16
LINE A
Note: "P" in assembly line position AS SEMBLY
indicates "Lead-Free" LOT CODE
"P" in assembly line position indicates
"Lead-Free" qualification to the consumer-level

PART NUMBER
INTERNATIONAL
OR RECTIFIER IRFR120
DATE CODE
P = DESIGNATES LEAD-FREE
LOGO PRODUCT (OPTIONAL)
12 34
P = DESIGNATES LEAD-FREE
ASS EMBLY PRODUCT QUALIFIED TO THE
CONSUMER LEVEL (OPTIONAL)
LOT CODE
YEAR 1 = 2001
WEEK 16
A = AS SEMBLY S ITE CODE

Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
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IRFR/U3505PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

EXAMPLE: T HIS IS AN IRF U120 PART NUMBER
INT ERNATIONAL
WIT H AS SEMBLY
RECTIF IER IRFU120 DAT E CODE
LOT CODE 5678
LOGO 119A YEAR 1 = 2001
AS SEMBLED ON WW 19, 2001
56 78 WEEK 19
IN THE ASS EMB LY LINE "A"
LINE A
ASS EMBLY
LOT CODE
Note: "P" in ass embly line pos ition
indicates Lead-Free"

OR
PART NUMB ER
INT ERNATIONAL
RECTIFIER IRFU120 DAT E CODE
LOGO P = DESIGNAT ES LEAD-F REE
56 78 PRODUCT (OPT IONAL)
YEAR 1 = 2001
ASSEMBLY
LOT CODE WEEK 19
A = ASSEMBLY SITE CODE

Notes:
1. For an Automotive Qualified version of this part please seehttp://www.irf.com/product-info/auto/
2. For the most current drawing please refer to IR website at http://www.irf.com/package/
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 IRFR/U3505PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)

TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) FEED DIRECTION 8.1 ( .318 )

FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
‚ Limited by TJmax, starting TJ = 25°C, L = 0.47mH † Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
RG = 25Ω, IAS = 30A, VGS =10V. Part not
recommended for use above this value.
ƒ ISD ≤ 30A, di/dt ≤ 300A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
„ Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
… Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
avalanche performance.
‡ This value determined from sample failure population. 100%
tested to this value in production.
ˆ When mounted on 1" square PCB (FR-4 or G-10 Material) .
For recommended footprint and soldering techniques refer to
application note #AN-994

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.09/2010
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