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    Ahmed Tarek
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    The document discusses cache performance metrics for a processor. It states that the processor has a static clock cycle time of 0.5 ns and that instructions are present in the cache 100% of the time, while 30% of instructions also require a cache access for data. This results in an average of 1.3 cache accesses per instruction. It also provides details on the cache hit rates, access times for transferring data between different cache levels, and bus specifications.

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    The document discusses cache performance metrics for a processor. It states that the processor has a static clock cycle time of 0.5 ns and that instructions are present in the cache 100% of the time, while 30% of instructions also require a cache access for data. This results in an average of 1.3 cache accesses per instruction. It also provides details on the cache hit rates, access times for transferring data between different cache levels, and bus specifications.

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    Download as PDF, TXT or read online from Scribd
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    4 views1 page

    Save Rage

    Uploaded by

    Ahmed Tarek
    The document discusses cache performance metrics for a processor. It states that the processor has a static clock cycle time of 0.5 ns and that instructions are present in the cache 100% of the time, while 30% of instructions also require a cache access for data. This results in an average of 1.3 cache accesses per instruction. It also provides details on the cache hit rates, access times for transferring data between different cache levels, and bus specifications.

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    Attribution Non-Commercial (BY-NC)
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    of 1

    CPI : Static time defined by the processor independent of the instruction type = 0.

    5 Number of cache accesses: o All instructions are present in cache, so we access the cache 100% of instructions o Some data may be loaded or stored from memory, this will need a cache access. 30% of instructions need this. Number of cache accesses is 130% = 1.3

    o o

    1 - h1 = 1 - 0.97 = 0.03 L2access time = 25 ns, but we need this time relative to the processor (in terms of clock cycles)

    Time needed to transfer a block from L2 to L1: We need to transfer a block of size 32 bytes using a bus of width 256 bits (32 bytes) at a speed of 500 Mhz

    o o o o Time needed to transfer a block from memory to L2: We need to transfer a block of size 64 bytes using a bus of width 128 bits (16 bytes) at a speed of 250 Mhz 1 - h1 = 1 - 0.97 = 0.03 1 - h2 = 1 - 0.9 = 0.1

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