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VLSI IEEE PROJECTS LIST

1. Design and Implementation of Viterbi Encoding and Decoding Algorithm on FPGA 1. A Multi-Standard Reconfigurable Viterbi Decoder using Embedded FPGA blocks 1. Low Power State-Parallel Relaxed Adaptive Viterbi Decoder Adaptive Viterbi Decoder

1. Fpga Implementation For Humidity And Temperature Remote Sensing

System

2. Based Multi-Interface Module (I2m) For Industrial Processes Automation

1. A configurable Motion Estimation Architecture for block matching

Algorithms. 2. A Fast VLSI Design of SMS4 Cipher Based on Twisted BDD S-Box Architecture. 3. FPGA based Implementation of High Performance Architectural level Low Power 32-bit RISC Core 4. FPGA Implementation of AES Encryption and Decryption(AES Algorithm). 5. Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST. VLSI IEEE 2010 PROJECTS 1. New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter. 2. Design of SHA-1 Algorithm based on FPGA 3. FPGA Implementation of efficient FFT algorithm based on complex sequence 4. Implementation of Non-Pipelined and Pipelined Data Encryption Standard (DES) Using Xilinx Virtex-6 FPGA Technology

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VLSI IEEE PROJECTS LIST
5. Algorithm Of Binary Image Labeling And Parameter Extracting Based On Fpga 6. A Pipeline Vlsi Architecture For High-Speed Computation Of The 1-D Discrete Wavelet Transform 7. 8. 9. Design Of A Low Power Flip-Flop Using Cmos Deep Submicron Technology An Fpga-Based Architecture For Linear And Morphological Image Filtering Dual Stack Method A Novel Approach To Low Leakage And Speed Power Product Vlsi Design Fpga Based Real-Time Adaptive Fuzzy Logic Controller Hardware Realization Of Shadow Detection Algorithm In Fpga Image Edge Detection Based On Fpga

10. 11. 12.

13.

Test Data Compression Using Efficient Bitmask And Dictionary Selection Methods 14. Concatenated Reed-Solomon Code with Hamming Code for DRAM Controller 15. Design and Implementation of a Parallel Processing Viterbi Decoder Using FPGA 16. General-Purpose FPGA Platform for Efficient Encryption and Hashing 17. Implementation of (15, 9) Reed Solomon Minimal Instruction Set Computing on FPGA using Handel-C 18. Implementing Rainbow Tables in High-end FPGAs for Super-fast Password Cracking 19. Prototyping Platform for Performance Evaluation of SHA-3 Candidates 20. A Low-Complexity Message-Passing Algorithm for Reduced Routing Congestion in LDPC Decoders

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VLSI IEEE PROJECTS LIST
21. A Reconfigurable Wireless Stepper Motor Controller Based On FPGA Implementation 22. An FPGA-Based Simulator for High Path Count Rayleigh and Rician Fading; 23. High Density FPGA Based Waveform Generation for Radars;

24. Low-Power Reconfigurable Acceleration of Robust Frequencydomain Echo Cancellation on FPGA 25. 26. PI-like Fuzzy Control Implementation using FPGA Technology Self-Adaptive Frequency Agility Realized with FPGA

VLSI IEEE 2011 PROJECTS

1.

A Median Filter Fpga With Harvard Architecture Detecting Background Setting For Dynamic Scene

2.

3. Design And Fpga Implementation Of Modified Distributive Arithmetic Based Dwt-Idwt Processor For Image Compression 4. A Lightweight High-Performance Fault Detection Scheme For The Advanced Encryption Standard Using Composite Fields 5. A Rotation-Based Bist With Self-Feedback Logic To Achieve Complete Fault Coverage 6. Adiabatic Technique For Energy Efficient Logic Circuits Design 7. Efficient Weighted Modulo 2n+1 Adders By Partitioned Parallel Prefix Computation And Enhanced Circular Carry Generation 8. An Autonomous Vectorscalar Floating Point Coprocessor For Fpgas 9. Design And Characterization Of Parallel Prefix Adders Using Fpgas

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VLSI IEEE PROJECTS LIST
10. High Speed Asic Design Of Complex Multiplier Using Vedic Mathematics 11. High-Accuracy Fixed-Width Modified Booth Multipliers For Lossy Applications 12. Implementation And Performance Analysis Of Seal Encryption On Fpga, Gpu And Multi-Core Processors 13. Lossless Implementation Of Daubechies 8-Tap Wavelet Transform 14. A fully pipelined implementation of Monte Carlo based SSTA on FPGAs 15. 16. An Efficient Implementation of Floating Point Multiplier High Level Power Estimation Models for FPGAs

17. Design and Complexity Analysis of Reed Solomon Code Algorithm for Advanced RAID System in Quaternary Domain 18. FPGA Implementation of Modified Architecture for Adaptive Viterbi Decoder 19. Inter-Packet Symbol Approach To Reed-Solomon FEC Codes For RTP-Multimedia Stream Protection 20. Novel Hardware Architecture for implementing the inner loop of the SHA-2 Algorithms 21. A Flexible Hardware Implementation of SHA-1 and SHA-2 Hash Functions 22. Design of Low Power Column Bypass Multiplier using FPGA

23. FPGA implementation of modified architecture for adaptive Viterbi decoder 24. Design of FPGA-Based Traffic Light Controller System

VLSI IEEE 2012 PROJECTS

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VLSI IEEE PROJECTS LIST
1. High-Speed Low-Power Viterbi Decoder Design For Tcm Decoders 2. A New Fault Injection Approach for Testing Network-on-Chips 3. An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithm 4. Channel Estimation Algorithms for OFDMIDMA High-Valency Ling Adders 5. Design and implementation of an optical OFDM baseband receiver in FPGA 6. Design and Implementation of High-Performance HighValency Ling Adders 7. Design and implementation of Reed Solomon Decoder for 802.16 network using FPGA 8. Design and Realization of Serial Front Panel Data Port (SFPDP) Protocol 9. Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA implementation 10. Efficient VLSI implementation of soft-input soft-output fixed-complexity sphere decoder 11. FPGA Based Controller for Large Port Count Optical Packet Switches 12. 1FPGA Implementation of 16 bit BBS and LFSR PN Sequence Generator A Comparative Study 13. FPGA Implementation of BASK-BFSK-BPSK Digital Modulators 14. FPGA Implementation of Chaotic Pseudo-Random Bit Generators 15. Implementation of DFT filter banks based on FPGA

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VLSI IEEE PROJECTS LIST
16. Implementation of VLSI-Oriented FELICS Algorithm Using Pseudo Dual-Port RAM 17. Performance Analysis of MC-CDMA System

18. Relaxed Fault-Tolerant Hardware Implementation of Neural Networks in the Presence of Multiple Transient Errors 19. VLSI Implementation of a Bio-Inspired Olfactory Spiking Neural Network

VLSI IEEE No Year PROJECTS

1.

Area and Power Efficient VLSI Architecture for DCT

2. Design of 64-bit low power parallel prefix VLSI adder for high speed arithmetic circuits 3. Low power dissipation using FPGA architecture 4. Low-power dissipation using FPGA architecture 5. Generalized Secure Hash Algorithm SHA-X

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