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Outline

Introduction Is there a limit? Transistors CMOS building blocks Parasitics I The [un]desirables Parasitics II Building a full MOS model The CMOS inverter A masterpiece Technology scaling Smaller, Faster and Cooler Technology Building an inverter Gates I Just like LEGO The pass gate An useful complement Gates II A portfolio Sequential circuits Time also counts! DLLs and PLLs A brief introduction Storage elements A bit in memory
The pass gate 1

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An useful complement
The pass gate switch Regions of operation Pass gate delay

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The pass gate

The CMOS pass gate

C n-switch C 0 0 1 1 A 0 1 0 1 Y ? ? good 0 good 1

A p-switch C

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The pass gate

The CMOS pass gate


Regions of operation: 0 to 1 transition NMOS:
source follower Vgs = Vds always:
Vout < Vdd-VTN saturation Vout > Vdd-VTN cutoff
Pass gate: 0 => 1 transition V dd
in 1 0 t

out 1 0 t

in

out

0V Equivalent for 0 = > 1 transition Vdd

VTN > VTN0 (bulk effect)

PMOS:
current source Vout < |VTP| saturation Vout > VTP linear
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out "Current source" "Source follower"

The pass gate

The CMOS pass gate


Pass gate transient response 3 2.5
(V)

V out

2 1.5 1 0.5 0 -0.5 0 2 4 6 Time (ns) 8 10 12 V in

(mA)

Vin, V out (V)

0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 2 4 6 Time (ns) 8 10 12 I D(pmos) I D(nmos)

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ID(nmos), ID(pmos)

The pass gate

The CMOS pass gate


Regions of operation: 0 to 1 transition
Vout< |VTP| |VTP|< Vout < Vdd - VTN Vout > Vdd - VTN NMOS and PMOS saturated NMOS saturated, PMOS linear NMOS cutoff, PMOS linear

Regions of operation: 1 to 0 transition


Vout > Vdd - VTN Vdd - VTN > Vout > |VTP| VTP > Vout NMOS and PMOS saturated NMOS linear, PMOS saturated NMOS linear, PMOS cutoff

Both devices combine to form a good switch


Paulo Moreira The pass gate 6

The CMOS pass gate


Delay of a chain of pass gates:

t d C Req

N ( N + 1) 2

Chain of transmission gates


Vdd Vdd Vdd Vdd

in
0V

1
0V

2
0V

3
0V

out

Delay proportional to N2 Avoid N large:


Break the chain by inserting buffers

Warning:
A pass gate provides no power gain or buffering All the work is done by the previous gate It really looks like a simple switch
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Equivalent delay model Req 1 Req 2 Req in

Req N

out

The pass gate