CD4023BC Buffered Triple 3-Input NAND Gate

October 1987 Revised August 2000

CD4023BC Buffered Triple 3-Input NAND Gate

General Description
These triple gates are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and Pchannel enhancement mode transistors. They have equal source and sink current capabilities and conform to standard B series output drive. The devices also have buffered outputs which improve transfer characteristics by providing very high gain. All inputs are protected against static discharge with diodes to VDD and VSS.

Features
s Wide supply voltage range: s Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74LS s 5V10V15V parametric ratings s Symmetrical output characteristics s Maximum input leakage 1 A at 15V over full temperature range 3.0V to 15V s High noise immunity: 0.45 VDD (typ)

Ordering Code:
Order Number CD4023BCM CD4023BCS CD4023BCN Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X tot he ordering code.

Connection Diagram

Block Diagram

/3 Device Shown

Top View

*All Inputs Protected by Standard CMOS Input Protection Circuit.

2000 Fairchild Semiconductor Corporation

DS005956

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CD4023BC

Absolute Maximum Ratings(Note 1)

(Note 2) DC Supply Voltage (VDD) Input Voltage (VIN) Storage Temp. Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260C 700 mW 500 mW

Recommended Operating Conditions

DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) 5 VDC to 15 VDC 0 VDC to VDD VDC

0.5 VDC to +18 VDC 0.5 VDC to VDD+0.5 VDC 65C to +150C

40C to +85C

Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The table of Recommended Operating Conditions and Electrical Characteristics provides conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified.

DC Electrical Characteristics (Note 3)

Symbol IDD Parameter Quiescent Device Current VDD = 5V VDD = 10V VDD = 15V VOL LOW Level Output Voltage VDD = 5V VDD = 10V VDD = 15V VOH HIGH Level Output Voltage VDD = 5V VDD = 10V VDD = 15V VIL LOW Level Input Voltage VDD=5V, VO=4.5V VDD=10V, VO=9.0V VDD=15V, VO=13.5V VIH HIGH Level Input Voltage VDD=5V, VO=0.5V VDD=10V, VO=1.0V VDD=15V, VO=1.5V IOL LOW Level Output Current VDD=5V, VO = 0.4V (Note 4) IOH VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V HIGH Level Output Current VDD = 5V, VO = 4.6V (Note 4) IIN Input Current VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V
Note 3: VSS = 0V unless otherwise specified. Note 4: IOH and IOL are tested one output at a time.

Conditions

40C Min Typ 1.0 2.0 4.0 0.05 0.05 0.05 4.95 9.95 14.95 1.5 |IO|<1A 3.5 |IO|<1A 7.0 11.0 0.52 1.3 3.6 0.52 1.3 3.6 0.3 0.3 3.0 4.0 3.5 7.0 11.0 0.44 1.1 3.0 0.44 1.1 3.0 4.95 9.95 14.95 Min

+25C Typ 0.004 0.005 0.006 0 0 0 5 10 15 2 4 6 3 6 9 0.88 2.2 8 0.88 2.2 8 105 105 0.3 0.3 1.5 3.0 4.0 Max 1.0 2.0 4.0 0.05 0.05 0.05

+85C Min Max 7.5 15 30 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.36 0.90 2.4 0.36 0.90 2.4 1.0 1.0

Units

mA

mA

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CD4023BC

AC Electrical Characteristics
Symbol tPHL Parameter Propagation Delay, HIGH-to-LOW Level

(Note 5)
Conditions VDD = 5V VDD = 10V VDD = 15V Min Typ 130 60 40 110 50 35 90 50 40 5 17 Max 250 100 70 250 100 70 200 100 80 7.5 pF pF ns ns ns Units

TA = 25C, CL = 50 pF, RL = 200k, unless otherwise specified

tPLH

Propagation Delay, LOW-to-HIGH Level

VDD = 5V VDD = 10V VDD = 15V

tTHL, tTLH CIN CPD

Transition Time

VDD = 5V VDD = 10V VDD = 15V

Average Input Capacitance Power Dissipation Capacity (Note 6)

Any Input Any Gate

Note 5: AC Parameters are guaranteed by DC correlated testing. Note 6: CPD determines the no load AC power consumption of any CMOS device. For complete explanation, see Family Characteristics Application Note AN-90.

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CD4023BC

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

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CD4023BC

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

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CD4023BC Buffered Triple 3-Input NAND Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A

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