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VLSI Design Methodology

Outlines
VLSI Design Flow and Structural Design Principles VLSI Design Styles VLSI Design Strategies Computer-Aided Design Technology for VLSI

Nitin Chaturvedi

VLSI Design Methodology

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Design Domains

Nitin Chaturvedi

VLSI Design Methodology

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Simplified VLSI Design Flows System Specification Circuit Representation Behavioral Representation Functional (Architecture) Design Circuit Design Functional Verification Logic (Gate(Gate -Level) Representation Circuit Verification Logic Design Physical Design Layout Representation Logic Verification Physical Verification Front End Synthesis Phase Nitin Chaturvedi Back End Layout Phase 4 VLSI Design Methodology .

Design Abstraction level Nitin Chaturvedi VLSI Design Methodology 5 .

Gates Circuit (Transistor(Transistor -Level) Representation Transistor Schematics Layout Representation Nitin Chaturvedi Physical Devices VLSI Design Methodology 6 . FSM Logic (Gate(Gate-Level) Representation Logic Blocks.Four Levels of Design Representation Behavioral Representation Functional Blocks.

Structure Design Principles Hierarchy: “Divide and conquer” technique involves dividing a module into sub-modules and then repeating this operation on the submodules until the complexity of the smaller parts becomes manageable. Regularity usually reduces the number of different modules that need to be designed and verified. but also similar blocks. Regularity: The hierarchical decomposition of a large system should result in not only simple. Nitin Chaturvedi VLSI Design Methodology 7 . as much as possible. at all levels of abstraction.

Nitin Chaturvedi VLSI Design Methodology 8 .Example of Regularity These circuits are built using inverters and tritri-state buffers only.

Modularity allows each block to be designed independently. avoiding longlong-distance connections as much as possible. The concept of locality also ensures that connections are mostly between neighboring modules.) Modularity: The various functional blocks which make up the larger system must have well well-defined functions and interfaces.Structured Design Principles (Cont. Nitin Chaturvedi VLSI Design Methodology 9 . Locality: Internal details remain at the local level. All blocks can be combined with ease at the end of the process.

Example: 16 16-bit Adder Circuit Structural Hierarchy of a 16 16-bit Manchester Adder Nitin Chaturvedi VLSI Design Methodology 10 .

Example (Cont.): Level 1 16-bit Adder 16Complete Layout 4-bit Adder with Manchester carry Nitin Chaturvedi VLSI Design Methodology 11 .

): Level 2 Carry/propagate circuit Output buffer/latch Manchester Carry circuit 4-bit Adder with Manchester Carry Layout Nitin Chaturvedi VLSI Design Methodology 12 .Example (Cont.

Example (Cont.): Level 3 Carry/propagate circuit layout Manchester carry circuit layout Output buffer/latch circuit layout Nitin Chaturvedi VLSI Design Methodology 13 .

Outlines VLSI Design Flow and Structural Design Principles VLSI Design Styles VLSI Design Strategies Computer-Aided Design Technology for VLSI Nitin Chaturvedi VLSI Design Methodology 14 .

VLSI Design Styles Nitin Chaturvedi VLSI Design Methodology 15 .

Nitin Chaturvedi VLSI Design Methodology 16 .

Nitin Chaturvedi VLSI Design Methodology 17 .FullFull -Custom Design Full-custom blocks are carefully crafted in the physical level to obtain the highest possible performance.

Nitin Chaturvedi VLSI Design Methodology 18 . especially if the low level regularity is not well defined.FullFull -Custom Design Key Issues The key to Full-custom design is to exploit the fine-grained regularity and modularity in the physical level. Manual full-custom design can be very challenging and time consuming. Development cost are too high! Design reuse is becoming popular to reduce design cycle time and development cost. IP blocks Full-custom design is used only in the critical blocks.

FullFull -Custom DRAM Example Nitin Chaturvedi VLSI Design Methodology 19 .

Library contains a certain numbers of basic cells such as inverters. Most popular because of CAD tools availability and capability. each in several versions to provide a range of performance. Nitin Chaturvedi VLSI Design Methodology 20 . and quadruple size. double size. NAND. The inverter gate can have standard size.CellCell -Based Design “Lego” Style Design All of the commonly used logic cells are developed. characterized. and stored in a standard cell library. NOR.

Most advanced CAD tools have place-and-route tools. In a complex. Standard Library. Most challenging task is to how to place the individual cells into rows and interconnect them in a way that meet stringent design goals. then full-custom design where necessary. Low Power Library. standard-cell based design approach may be used as a first pass. Nitin Chaturvedi VLSI Design Methodology 21 . demanding design.CellCell -Based Design Key Issues Inclusion/Exclusion of a gate variation depends on the objectives of the library. etc.

Nitin Chaturvedi VLSI Design Methodology 22 .Example of Standard Cells Power Rail Ground Rail Each cell layout is designed with a fixed height so that a number of cells can be “snapped” together sideside-by by-side to form rows.

) Standard Cell Routing Channel Nitin Chaturvedi VLSI Design Methodology 23 .Example of Stand Cells (Cont.

CellCell -Based Design Example Nitin Chaturvedi VLSI Design Methodology 24 .

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Masked Gate Array (MGA) Design Only transistors No contacts and metal layers One pattern mask for Mass production Nitin Chaturvedi VLSI Design Methodology 26 .

MGA Design Key Issues “Uncommitted” (Unused) transistors or gates are wasted. higher density. and routability Nitin Chaturvedi VLSI Design Methodology 27 . Uncommitted cells can be sacrifices to improve intercell routing capability Modern GAs use multiple metal layers for channel routing Smaller area. Performance measured as Chip Utilization Factor ~ used chip area/total chip area.

Example of MGA Design Nitin Chaturvedi VLSI Design Methodology 28 .

. Program interconnect switch matrices Program I/O blocks Programs last as long as the chip is powered-on Nitin Chaturvedi VLSI Design Methodology 29 . Program logic table for each logic block. a user can use high-level hardware programming (e. with programmable interconnects. organized into logic blocks.FPGA Design An FPGA chip provides thousands of logic gates. To implement a custom hardware. HDL).g.

Field Programmable Gate Array (FPGA) Architecture of Xilinx FPGAs Nitin Chaturvedi VLSI Design Methodology 30 .

FPGA (Cont.) Simplified block diagram of a CLB by Xilinx Nitin Chaturvedi VLSI Design Methodology 31 .

Synchronous and asynchronous Set/Reset H1 DIN S/R EC S/R Control G4 G3 G2 G1 G Func. Gen.Independent clock polarity . DIN F' G' H' SD D Q YQ 1 G' H' S/R Control EC RD Y F4 F3 F2 F1 DIN F' G' H' SD D Q XQ EC 1 H' F' RD X K . H Func.XC4000 XC4000E E Configurable Logic Blocks C1 C2 C3 C4 2 Four-input function generators (Look Up Tables) .Each can be configured as Flip Flop or Latch . Gen.16x1 RAM or Logic function 2 Registers . F Func. Gen.

0 0 1 1 0 1 0 1 0 1 .dual port RAM 1 VLSI Design Methodology Nitin Chaturvedi . Capacity is limited by number of inputs. Gen.Look Up Tables Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB Look Up Table Example: A B C D Z Combinatorial Logic 4-bit address A B C D 0 0 0 0 0 0 0 0 0 0 1 1 . 0 1 0 1 0 0 0 1 33 Z 0 0 0 1 1 1 WE G4 G3 G2 G1 G Func. not complexity 1 Choose to use each function 1 generator as 4 input logic (LUT) or as 1 high speed sync. 1 1 1 1 0 0 1 1 0 0 .

FPGA (Cont.) Switch matrices and interconnection routing between CLB Nitin Chaturvedi VLSI Design Methodology 34 .

but for small-volume production and for fast prototyping Nitin Chaturvedi VLSI Design Methodology 35 .Size of logic block Routing capability .Size of switch matrices The largest advantage of FPGA-based design is the very short turn turn-around time The time required from the start of the design process until a functional chip is available Typical price of FPGA chips is usually higher than other alternatives of the same design.FPGA Design Key Issues Chip utilization of an FPGA depends on Granularity of the logic block .

1990’s 1990 ’s The increasing computation power led to the introduction of logic synthesizers that can translate the description in HDL into a synthesized gate-level net-list of the design. Nitin Chaturvedi VLSI Design Methodology 36 .HDLHDL -Based Design 1980’s 1980 ’s Hardware Description Languages (HDL) were conceived to facilitate the information exchange between design groups. 2000’s 2000 ’s Modern synthesis algorithms can optimize a digital design and explore different alternatives to identify the design that best meets the requirements.

HDLHDL -Based Design Methodology Nitin Chaturvedi VLSI Design Methodology 37 .

Synthesis flow High-Level Synthesis Logic Synthesis Physical Design Fabrication and Packaging Nitin Chaturvedi VLSI Design Methodology 38 .

Outlines
VLSI Design Flow and Structural Design Principles VLSI Design Styles VLSI Design Strategies Computer-Aided Design Technology for VLSI

Nitin Chaturvedi

VLSI Design Methodology

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VLSI Design Strategies
Phenomenal growth rate in VLSI leads to a very complex and lengthy development of ICs.
Design complexity increases almost exponentially with the number of transistors to be integrated.

Efficient organization of all efforts is essential to the survival of a company.
Teamwork Better tools Innovatives and creativities. Better Strategies
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Product LifeLife-Cycle

Products have a shorter lifelife-cycle
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Comparison of Design Strategies Freedom of Choices…. Custom Design Nitin Chaturvedi VLSI Design Methodology 42 .

Comparison (Cont.) Cell Design FPGA Design Nitin Chaturvedi VLSI Design Methodology 43 .

rather than building a conventional printed circuit board. Consequences: More compact system realization Less expensive! Higher speed / performance Better reliability Nitin Chaturvedi VLSI Design Methodology 44 .SystemSystem -On On-Chip (SOC) Design Integrating all or most of the components of a hybrid system on a single substrate (silicon or MCM).

Example of SOC Design Digital Video Processor Nitin Chaturvedi VLSI Design Methodology 45 .

Nitin Chaturvedi VLSI Design Methodology 46 .Example of SOC Design (Cont. or customcustom-designed block.) Each functional block can be reused block. IP (Intelectual Property) block.

Outlines VLSI Design Flow and Structural Design Principles VLSI Design Styles VLSI Design Strategies ComputerComputer -Aided Design Technology for VLSI Nitin Chaturvedi VLSI Design Methodology 47 .

not the creative and inventive parts! CAD technology divides into three categories: Synthesis Tools (Synopsys®) Layout Tools (Cadence®) Simulation and Verification Tools Nitin Chaturvedi VLSI Design Methodology 48 .ComputerComputer -Aided Design Technology CAD tools become more and more indispensable for timely development of ICs. Remember! CAD tools are good helpers for timetime -consuming and computation intensive mechanistic parts of the design.

low power. Verilog. etc.Synthesis Tools High-Level Synthesis tools automate the design Highphase in the top level of the design hierarchy: Based on Hardware-Description Languages (HDL) VHDL. etc. Nitin Chaturvedi VLSI Design Methodology 49 . Logic Synthesis and optimization tools can then be used to customize the design to particular needs. Determining the types and quantities of modules to be included in the design using accurate estimate of lower level design features (area and delay). such as area minimization.

i.Layout Tools Circuit Optimization tools deal with the design in the transistor schematic levels: Transistor sizing for delay minimization Reliability issues: process variations. Place-and-route. noise. how circuits are actually built on the IC: Standard Layout CAD tools are Floorplanning.e. Layout tools concern with the physical level of the design.. and Module generation Sophisticated Layout CAD tools are goal driven and include some degree of optimization functions Nitin Chaturvedi VLSI Design Methodology 50 .

Simulation and verification are the most mature area in VLSI CAD Goal of all simulation tools is to determine if the design meets the required specifications at a particular design stage. Nitin Chaturvedi VLSI Design Methodology 51 .Simulation and Verification Tools Time spent on debugging and correcting a design has been increasing exponentially as each generation passed. Higher penalty is paid if a design flaw is detected later in the design process.

Simulation Tools (Cont. Design Rule Checking tools Layout rule checking. etc. PSPICE.) Simulation tools used at various stages of the design process are Behavior simulation tools Logic Level simulation tools Complement logic synthesis and optimization tools. reliability rule checking. Electrical Rule Checking (ERC). Nitin Chaturvedi VLSI Design Methodology 52 . CircuitCircuit -level simulation tools SPICE or derivatives such as HSPICE.

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Layout Standard Cell Module Chip Complete Design Nitin Chaturvedi VLSI Design Methodology 54 .

Placement and Routing Routing in FPGA Detailed Placement and Routing Nitin Chaturvedi VLSI Design Methodology 55 .

Chip Fabrication GDS II Nitin Chaturvedi VLSI Design Methodology 56 .

World wide IC Foundary Centres Nitin Chaturvedi VLSI Design Methodology 57 .

International Technology Road Map Nitin Chaturvedi VLSI Design Methodology 58 .

World wide Semiconductor vendors Nitin Chaturvedi VLSI Design Methodology 59 .

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Conclusions Different levels of Abstractions VLSI Design Flow Design Methodologies Design Styles Nitin Chaturvedi VLSI Design Methodology 61 .