ECE

171 Winter 2011 Homework 5 1. [10] Does the circuit below have any logic hazards? If so, identify them and give a logic hazard- free function that is equivalent.

2. [10] What function F is implemented below. Give your answer in compact minterm form.

3. [10] What function is being implemented below? Give your answer in compact minterm form.

4. [10] The truth table for the function F(D,C,B,A) is given below. Use a 16-to-1 multiplexer (mux) to implement the function. Do not use any other gates.

5. [10] Implement the same function from problem 5 using an 8-to-1 mux. You may also use an inverter. 6. [10] What function is being implemented by the circuit below? Give your answer in compact minterm form.

7. [10] Implement the function ! ! , !, ! = (1,2,6,7) using a 4-to-1 multiplexer.

8. [20] Implement the following four functions using a 4 input, 4 output PAL as depicted below. Show the retained fuses (connections) with an X. You can do this directly on the diagram below (or on a copy).

w(A,B,C,D) =

(2,12,13) x(A,B,C,D) = (7,8,9,10,11,12,13,14,15) y (A,B,C,D) = (0, 2,3, 4,5, 6, 7,8,10,11,15) z (A,B,C,D) = (1, 2,8,12,13)

9. [15] Implement the function F2 depicted in the truth table below using a portion of a PAL3L3 (Note: the outputs will be complemented!). Assume each OR gate has a fan-in of 4. Show the AND/OR array and all connections. X Y Z F2 -------0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 10. [15] Refer to the diagram below (a) What kind of PLD is depicted below (be specific)?

(b) What functions are being implemented in this design? (c) Identify any shared product terms

11. [20] Use a single 3-to-8 decoder and two additional gates to implement the functions S X, Y, Z = 1,2,4,7) and C X, Y, Z = 3,5,67 .