Digital Logic and Processor

Experiment 5

BCD to 7-segment Decoder

A BCD to 7-segment Decoder generates 7 outputs from a BCD (4-bit) input for driving a 7-segment LED display device to display BCD digits. A 7-segment display consists of seven segments designated as a, b, c, d, e, f and g in a clockwise sequence, and a dot (p) for displaying the decimal point, if necessary, as shown in Fig. 4.1(a). In a 7-segment LED display, either all the anodes or all the cathodes of the LEDs in the seven segments are tied together and brought out at a single pin, and the device is accordingly called either a common-anode or a common-cathode display. In this experiment, we will use a common-cathode display, and so the common cathode terminal is connected to Gnd, and the Decoder outputs are applied through resistors placed in series with the anode of each segment, as indicated in Fig. 4.1(b). Note that each segment is lighted when the corresponding decoder output, also denoted by a, b, c, d, e, f and g, is HIGH. The objective of this experiment is to design, assemble and test a BCD to 7-segment Decoder generating these seven outputs. In order to keep the circuit reasonably simple, we will only consider the digits 0-7, generated from a 3-bit input B2B1B0. Digit 0 1 2 3 4 5 6 7 8 9
a f g e d c p Gnd b

OFF Segments g adefg cf ef ade be b defg e

All resistors 1k

g f e d a b c p

Decoder Outputs c d e

(a)

(b)

Fig. 4.1 Nomenclature and Organisation of a 7-segment LED Display 1. Construct the K-maps for the 7 output bits in terms of B 2, B1 and B0. These outputs can either be realised by 4-input multiplexers, using two of the three variables as. the select inputs of the multiplexers, and using the third variable to generate the data inputs, or by 2-input multiplexers, using one of the three variables as the select input of the multiplexers, and using the other two variables to generate the data inputs. Table 4.1 gives the former design, using B2B1 as the Select inputs S1S0 of the

multiplexers, and Table 4.2 gives the latter design, using B2 as the Select input S of the multiplexers. Read the K-maps along the rows and verify the expressions for the data inputs of the multiplexers listed in these two tables. Table 4.1. Design using 4-input multiplexers Output B2B1 (Input No.) 00 (X0) 01 10 11 (X1) (X2) (X3) a B0 1 B0 b 1 1 B0 c 1 B0 1 d B0 1 B0 e B0 B0 0 f B0 0 1 B0 f B1B0 B1+B0 g 0 1 1 B0 g B1 B1+B0

1 B0 1 B0 B0 Table 4.2. Design using 2-input multiplexers a B1+B0 B1+B0 b 1 B1B0 c B1+B0 1 d B1+B0 (B1B0) e B0 B1B0

Output B2 (Input No.) 0 (X0) 1 (X1)

2. Realise the outputs a, b, d and f with four 4-input multiplexers (two chips) and the outputs c, e and g with three 2-input multiplexers (one chip), considering the fact that the data inputs required for c, e and g are the easiest to generate. Generate the required data inputs of the 2-input multiplexers with three 2-input NAND gates, generating B0 from B0 with the fourth NAND gate available in the same IC : B1+B0 = (B1B0), B1B0 = ((B1B0)) and B1+B0 = (B1B0). 3. We will thus be using two dual 4-input multiplexer chips (74LS153), one quad 2-input multiplexer chip (74LS157) and one quad NAND chip (74LS00) for the complete circuit. The pin connections of the 74LS153 chip are given in Fig. 4.2. Following the usual notation, the data inputs are denoted by X 0, X1, X2, X3, the data output denoted by Q, and the (negative-logic) output enable input denoted by EN for each multiplexer, with 1 or 2 preceding the symbol to distinguish the two multiplexers. S 1 and S0 are the select inputs common to the two multiplexers. For each multiplexer, Q = Xn (selected data input) if S1S0 = n (in binary code) only if EN = 0, and Q =0 if EN = 1. Test the three given multiplexer chips one by one by connecting V CC and Gnd appropriately and applying EN and appropriate inputs from the Input Switches. Verify the multiplexer function by tabulating the values of the output(s) for all input combinations. Test all the four gates in the given 74LS00 chip..
16 15 14 S0 13 2X3 12 2X2 11 2X1 10 9

VCC 2EN

2X0 2Q

74LS153 1EN 1 S1 2 1X3 3 1X2 1X1 4 5 1X0 6 1Q Gnd 7 8

Fig. 4.2 Pin Connections of the Dual 4-input multiplexer 74LS153 IC 4. Implement the multiplexer-based design for the BCD to7-segment Decoder, applying B3, B2 and B0 from three Input Switches through the bus strips available in the breadboard. Use a fourth bus strip for B0, that is used at many places. Connect the

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seven outputs a, b, c, d, e, f and g generated by your circuit to the corresponding points in the circuit shown in Fig. 4.1 (b) to complete the assembly of the BCD to 7segment Decoder along with the 7-segment display. 5. Tabulate the digit displayed on the 7-segment display for all the 8 combinations of B3, B2 and B0.