CIRCUITS AND

6.002 ELECTRONICS

Digital Circuit

6.002 Fall 2000 Lecture 13 1

 Review

vI R +
VI vI +
– C vC
–
t
0
vC (0 ) = VO

−t
vC = VI + (VO − VI ) e RC 1

vC

VI

time constant RC
VO
t
RC

6.002 Fall 2000 Lecture 13 2

 Let’s apply the result to
an inverter.
A B
X
First, rising delay tr at B

VS VS

A
B
vA
5V CGS
X

t
0
1 Æ 0 at A

6.002 Fall 2000 Lecture 13 3

First, rising delay tr at B
VS VS

A
B

CGS
vA X
5V

t vB
0 5V ideal
1 Æ 0 at A observed
t
0

6.002 Fall 2000 Lecture 13 4

First, rising delay tr at B
VS VS

A
B
vA
5V CGS
X

t
0 vB
1 Æ 0 at A 5V
VOH

t
0 tr
rising delay of X

6.002 Fall 2000 Lecture 13 5

Equivalent circuit for 0Æ1 at B

RL +
vI = VS + CGS vB
– –

vI = VS
for t ≥ 0
vB (0 ) = 0

From 1
−t

vB = VS + (0 − VS ) e RL CGS

Now, we need to find t for which

vB = VOH .

6.002 Fall 2000 Lecture 13 6

 Or −t

vOH = VS − VS e RL CGS

Find tr :
−t r

VS e RL CGS
= VS − VOH

− tr VS − VOH
= ln
RL CGS VS

VS − VOH
t r = − RL CGS ln
VS

6.002 Fall 2000 Lecture 13 7

 Or −t

vOH = VS − VS e RL CGS

Find tr :
−t r

VS e RL CGS
= VS − VOH

− tr VS − VOH
= ln
RLCGS VS

VS − VOH
t r = − RL CGS ln
VS

e.g. RL = 1K VS = 5V
CGS = 0.1 pF VOH = 4V

−12 5−4
t r = −1 × 10 × 0.1 × 10
3
ln
5
= 0.16 ns
RC = 0.1 ns !
6.002 Fall 2000 Lecture 13 8
Falling Delay tf
Falling delay tf is
the t for which vB falls to VOL

Equivalent circuit for 1 Æ 0 at B

RL vB (0 ) = VS
(5V )
VS +
– +
CGS vB
RON –

6.002 Fall 2000 Lecture 13 9

 Falling Delay tf
Equivalent circuit for 1 Æ 0 at B

RL vB (0 ) = VS
(5V )
VS +
– +
CGS vB
RON –

X
Thévenin replacement …

RTH +
VTH +
– CGS vB
–

RTH = RL || RON
RON
VTH = VS
RON + RL
6.002 Fall 2000 Lecture 13 10
 From 1
−t

vB = VTH + (VS − VTH ) e RTH CGS

Falling decay tf is
the t for which vB falls to VOL

−t f

VOL = VTH + (VS − VTH ) e RTH CGS

VOL − VTH
or t f = − RTH CGS ln
VS − VTH

6.002 Fall 2000 Lecture 13 11

 VOL − VTH
t f = − RTH CGS ln
VS − VTH

e.g. RL = 1K VS = 5V RON = 10Ω

CGS = 0.1 pF VOL = 1V
RTH ≈ 10Ω, VTH ≈ 0V
−12 1
t f = −10 ⋅ 0.1 ⋅10 ln
5
= 1.6 ps
RC = 1 ps !

6.002 Fall 2000 Lecture 13 12

For recitation: Slow may be better
Problem

chip
pin 2
pin 1 v

CL

v:
ideal observed slow!

So the engineers decided to speed it up…

RL made RL small
RON made RON small

6.002 Fall 2000 Lecture 13 13

For recitation: Slow may be better
Problem

chip
pin 2
pin 1 v

CL

v:
ideal observed slow!

… but, disaster!
v: observed
expected
VIL

6.002 Fall 2000 Lecture 13 14

 Why? Consider … Demo
Case 1 R1

pin1
R0
ok

6.002 Fall 2000 Lecture 13 15

 Why? Consider … Demo
Case 2 CP
R1

pin1 pin2
R0
R2

crosstalk!
CP

R +
v +
model for crosstalk: –
–

6.002 Fall 2000 Lecture 13 16

 Case 3

… 6.002 expert saw the solution

CP
R1

+
R0 –
R2

slower transitions!

Detailed analysis in recitation.

6.002 Fall 2000 Lecture 13 17