Small Time-Step Tutorial

Small Time-Step Simulation
An Introductory Tutorial
BRDG1
1
2
3
4
5
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TABLE OF CONTENTS

1 INTRODUCTION ..................................................................................................................................... 3
2 SMALL TIME-STEP SIMULATION BASICS ............................................................................................... 4
3 SIMPLE VOLTAGE RECTIFIER ................................................................................................................. 8
4 SIMPLE STATCOM EXAMPLE ............................................................................................................... 15
5 INTERFACING LARGE AND SMALL TIME-STEP SIMULATIONS ............................................................. 30
6 CONNECTING VSC BRIDGE BOXES USING SMALL TIME-STEP TRANSMISSION LINES ......................... 34
7 SMALL TIME-STEP IO ........................................................................................................................... 39
8 SELECTING VALVE PARAMETERS ......................................................................................................... 45
9 DISTRIBUTING PROCESSING LOAD OVER TWO PROCESSORS ............................................................. 49
10 REFERENCES .................................................................................................................................... 51

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1 INTRODUCTION

Typical time-steps for EMTP type simulations are on the order of 50 microseconds. Such time-steps, however,
are not sufficiently small to allow for the accurate simulation of high frequency switching circuits such as those
used in PWM schemes. In order to model such schemes a feature known as small time-step simulation was
introduced into RSCAD. Small time-step simulation uses several shortcuts in order to reduce the time-step
down to somewhere in the neighbourhood of 1.5 to 2.5 microseconds. The actual time-step is not directly
controlled by the user but is a function of the complexity of the circuit being simulated. The aim of this tutorial is
to familiarize the user with the small time-step simulation feature of the RTDS Simulator.

This tutorial is broken up into several parts. In section 2 some of the basic theory behind small time-step
simulation is provided. Next, some of the details involved in building a small time-step case are shown; this is
done primarily by means of example. First a simple voltage rectifier is built in section 3 and then a simplified
STATCOM is assembled in section 4. The aim of sections 3 and 4 is to assist the reader in assembling a working
simulation case. Sections 5 through 9 will introduce some more advanced topics. Section 5 details how a small
time-step simulation circuit can be interfaced with a large time-step circuit. Section 6 will explain how increase
the size of a circuit simulated using the small time-step simulation facility. Section 7 deals with importing and
exporting digital and analog signals into and out of the simulation. Section 8 discusses strategies for how to go
about selecting the valve parameters. Finally, in section 9 details are given on how to spread the processing load
of the small time-step simulation over multiple processors.

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2 SMALL TIME-STEP SIMULATION BASICS

In order to understand small time-step simulation it is important to understand some fundamentals about the core
solution algorithm used by the RTDS Simulator. Consider the simple circuit of Figure 2.1A for a moment. It
consists of a source and three series connected conductances (g
1
, g
2
and g
3
). If the source and g
1
are converted
to their Norton equivalent the circuit can be redrawn as shown in the adjacent figure of 2.1B. The labels V
1
and
V
2
are added to the circuit; our objective is to solve for these voltages.

Kirchhoffs Current Law (KCL) can be used to write the nodal equations at V
1
and V
2.
This results in Eq. 2.1 and
Eq. 2.2.

1
1
+ (
1

2
)
2
=
1
() [ Eq. 2.1 ]

2
3
+ (
2

1
)
2
= 0 [ Eq. 2.2 ]
These equations can be re-written in matrix form as shown in Eq. 2.3.

1
+
2
2
+
3

2
=
1
()
0
[ Eq. 2.3 ]
Solving for the node voltages V1 and V2 leads to Eq. 2.4 or equivalently Eq. 2.5.

2
=
1
+
2
2
+
3
1
()
0
[ Eq. 2.4]
[] = []
1
[] [ Eq. 2.5 ]
The voltages at both nodes can be calculated if the voltage source signal, V(t), along with the conductances g
1
, g
2

and g
3
are known. Eq. 2.5 is a very simplified summary of calculations carried out by the RTDS Simulator. In the
equations above, G is known as the conductance matrix. In general a circuit with N single phase nodes will lead
to a conductance matrix of N x N dimension.
g
2

V(t)
g
1

g
3

+
-
g
2

g
1
V(t)
g
1
g
3

+
-
V
2

V
1

(B) (A)
Figure 2.1: Simple circuit used to demonstrate RTDS solution algorithm
-5-

Without proof it is stated that passive elements such as inductors and capacitors can be modeled as current
sources connect in parallel with conductances. Figure 2.2 shows the equivalent circuits for inductors and
capacitors.

Furthermore, complicated elements such as Transformers, Transmission lines and Generators can also generally be
modeled as current sources connected in parallel with a conductance. Once all the elements in a circuit are
converted to a parallel conductance and current source, KCL can again be written for each of the nodes in the
circuit and an equation similar in form to that of Eq. 2.5 can be written. This is the general approach that the
RTDS Simulator uses. The true complication comes in trying to accurately model the behaviour of physical devices
by modeling them as a parallel connected current source and conductance.
One of the primary uses of the RTDS Simulator is its ability to study the transient behaviour of powers systems. It
is important to understand how a power system responds when a breaker opens/closes, when a fault occurs or is
cleared or when a power electronic device misfires. Fortunately, the framework developed above can easily
accommodate simulation of these conditions/scenarios.
Consider the circuit of Figure 2.3A which contains two series connected resistances and a switch which can open or
close. A switch can be modeled fundamentally as a conductance which is small when the switch is open and
large when the switch is closed. Given this realization the circuit of Figure 2.3A can be rewritten as shown in
Figure 2.3B. This circuit is identical to the circuit developed in Figure 2.1A thus the node voltages can be solved
for using Eq. 2.5. The primary difference will be that the conductance matrix, G, will evolve with time. When
the switch is in an open state the conductance g
3
will be small, conversely when the switch is in a closed state g
3
will be large. A time-varying conductance can just as easily be used to model a fault, or a power electronic
switch.

R
2

V(t)
R
1

S
1

+
-
g
2

V(t

g
1

g
3

+
-
V
1
V
2
V
2
V
1

(A)
(B)
L
+
-
v
L
(t)
i
L
(t)
IH
L
v
L
(t) g
L
+
-
i
L
(t)
+
-
v
C
(t)
i
C
(t)
IH
C
v
C
(t) g
C
+
-
i
C
(t)
(A) (B)
Figure 2.2 : Equivalent Circuits for (A) Inductor and (B) Capacitor
Figure 2.3: Circuit demonstrating the modeling of switches in large time-step simulations
-6-

The Challenge. . .
Anytime the switching state of the circuit changes, the G-matrix changes. Whenever the G-matrix changes, its
inverse will also need to be recalculated. Unfortunately, the number of operations needed to invert an N x N
matrix increases exponentially with N. Currently the effective inversion of a 66 node G matrix takes on the order
of 50s. Given the real-time constraint applied to the RTDS Simulator, it is not difficult to imagine that a 25 fold
increase in processing power would be needed in order to use the above described method to model switches
with the 2s time-step range necessary to accurately model some power electronic circuits. This is the challenge
that must be overcome in order to complete a real-time electromagnetic simulation using a time-step on the order
of 2s.
The Solution. . .
Given the challenges listed above, an alternate method for modeling a switch is needed. Instead of modeling
an open circuit as a small conductance it will be modeled as a series connected resistor and capacitor. Also,
instead of modeling a short circuit as a large conductance it will be modeled as an inductor.

It is possible, again without proof, to simplify the circuits chosen to represent a short circuit and an open circuit
into equivalent parallel connected current sources and conductances. Figure 2.4A and Figure 2.4B show the small
time-step representations for a short circuit and an open circuit respectively. These representations can easily be
incorporated into the above discussed formulation used to solve for node voltages. Changing the state of a
switch now involves two possible changes. First g
sc
is changed to g
oc
or vice versa; secondly, IH
sc
is changed to
IH
oc
or vice versa. Up to this point one approximation of an open circuit and another for a short circuit has been
proposed but neither the validity nor the advantages of such approximations have been discussed.
The validity of the approximation is the most pressing concern; the values of R and C must be selected so that
together they represent a fairly large impedance across the system bandwidth. Similarly, L must be selected so
that it represents a fairly small impedance across the system. If these criteria are not met then the chosen
approximations for a short circuit and an open circuit are invalid and there is no point in continuing with this
approach. Fortunately, it is possible to choose R, C and L to meet these constraints.
L
+
-
v
SC
(t)
i
SC
(t) +
-
IH
sc
v
sc
(t)
g
sc
i
sc
(t)
v
oc
(t)
IH
oc
g
oc
+
-
i
oc
(t) i
OC
(t)
+
-
v
OC
(t)
Short Circuit: Open Circuit:
(B)
(A)
Figure 2.4: Equivalent circuits used to represent (A) Short Circuit and
(B) Open Circuit in the small-time step simulation.

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In addition to being selected so that the constraints above are met, the parameters R, L and C can also be chosen
in such a way that g
sc
and g
oc
are equal. If g
sc
equals g
oc
then the conductance matrix of the system being
simulated will not change when the state of a switch changes. This in turn implies that the conductance matrix
remains constant throughout the entire simulation and that it does not need to be re-inverted when a switching
event occurs. Only the values of IH
sc
and IH
oc
need to be recalculated. This approach results in huge
computational savings and is the primary reason the time-step can be reduced to within the 1.5 2.5s range.
There are, however, disadvantages to this approach. The problem lies in the fact that open and short circuits are
being represented using capacitors and inductors, both energy storage devices. In either of the two states a
small amount of energy from the system will be stored, something which doesnt occur when using a pure
conductance to represent the open and short circuited conditions. Upon the occurrence of a switching event one
circuit representation is abruptly changed to the other and in doing this the small amount of energy that was
stored in the previous switching state is effectively discarded. This is an artificial energy loss that is introduced by
the modeling method and the total energy loss increases as the number of switching events increases. Switches
modeled in the above described manner can be operated up to about 3 kHz without problem but beyond this
frequency the artificial losses become unrealistic. Some of the small time-step models can be switched at
increased rates of up to 12 kHz but these switches have been modeled using the traditional method and are
mathematically decoupled from the small time-step G-matrix. This will be discussed later in this tutorial.
What has been presented so far was intended to give the user a basic understanding of the fundamentals of small
time-step simulation; further details about the above described approaches can be found in [1]. In the next
section, a simple voltage rectifier circuit will be assembled using the RTDS Simulators small time-step simulation
facilities.
-8-

3 SIMPLE VOLTAGE RECTIFIER

In this section a simple voltage rectifier will be assembled and simulated using the small time-step functionality of
the RTDS Simulator. The topology of the circuit will be similar to that shown in Figure 3.1. Since switching will
only occur at power system frequency this is not an example of the type of circuit that would typically need to be
studied using small time-step simulations but construction of this circuit is instructive nevertheless and serves as a
good starting point.

VSC Bridge Box
In order to build a small time-step simulation case the first thing that must be done is to add a special hierarchy
box into the DRAFT case. This special hierarchy box is known as a VSC Bridge Box and appears as shown in Figure
3.2. Any circuit which is to be simulated using a small time-step must be assembled inside a VSC Bridge Box. In
general, only small time-step components can be placed inside the VSC bridge box; large time-step component will
not work using a small time-step. The Master library contains a tab labelled Small_dt which contains a collection
of small time-step models. Although control compiler components can be placed within a VSC bridge box
without generating a compile error, they are nonetheless simulated using the large time-step.

Figure 3.1: Simple voltage rectifier circuit to be assembled.
Figure 3.2: Icon for the small time-step bridge box.
-9-

Double-clicking on a VSC bridge box allows its contents to be edited in the same manner that the contents of a
hierarchy box can be modified. Right-clicking on the VSC bridge box and selecting Edit->Parameters opens the
parameter menu; Figure 3.3 shows the parameter menu for the small time-step bridge box. Some of these
parameters will be described later in this tutorial but additional details can be found in the VSC Small Time-Step
Modelling Chapter of the manual.

Voltage Rectifier Circuit
Inside the VSC bridge box the circuit of Figure 3.4 should be constructed. It is a simple voltage rectifier where the
diode bridge has been replaced by a GTO bridge with anti-parallel diodes. If firing pulses for the GTOs are not
provided then the GTO bridge effectively becomes a diode bridge. The load on the DC bus will be a 100
resistance and the source impedance will be a 1 resistance. The six GTOs with anti-parallel diodes are a single
component named rtds_vsc_PH3LEV2 which can be found in the small time-step library.

Figure 3.3: Parameter menu for the rtds_vsc_BRIDGE_BOX
Figure 3.4: DRAFT model of rectifier circuit
-10-

When building small time-step circuits one component that is very useful is the rtds_vsc_BRC3 branch component.
This component is highly customizable and can be used to model R, L, C, RL, RC, RRL and high pass filter branches.
The number of branches per component can be varied between one and three and they can be positioned either
inline or in parallel. It is also possible to include a controlled voltage source in the branch by setting the vsrc
parameter to Yes as shown in Figure 3.5. The shape and magnitude of the voltages follow that of the controls
compiler signals referenced under the NAMES FOR REAL/INT VOLTAGE SOURCE INPUTS tab.

The AC side of the bridge has a three phase controlled voltage source so some external signals from the controls
compiler must be referenced. The control logic shown in Figure 3.6 will generate a set of three phase signals
which are assigned to SRCa, SRCb, SRCc. The source magnitude is 11.5 kV LL rms.

Five nodes are included in the circuit; three on the AC side and one at each rail of the DC side. It should be noted
that small time-step nodes differ from large time-step nodes in that their values are only monitored if explicitly
requested. Only the node voltages of interest should be monitored; for this example the voltages at all the nodes
should be monitored.
In order to achieve rectifier operation, no firing pulses are provided to the GTOs/IGBTs connected in anti-parallel
with the diodes. This can be done by changing the source of the firing pulses of the bridge to CC_WORD, naming
Figure 3.5: Adding voltage sources to a branch component
Figure 3.6: Control signals which generate the AC voltage signal
-11-

the control signal which serves as the control word for the bridge and assigning zero to that control word. The
least significant bit of the control word (bit 0) controls switch 1, the second least significant bit (bit 1) controls
switch 2 and so on. Figure 3.7 shows the menu items of the bridge which must be modified.

When the case is compiled the warning listed below might appear. This warning is to inform the user that there
might be a problem with their control circuitry because they are trying to control the switching of the bridge
elements use a gating signal that originates from the large time-step. This fundamentally undermines the
advantages of small time step simulation. For the moment this warning can be safely ignored because the
GTOs/IGBTs are not being switched during the simulation and there is no need for precise timing of the gating
signals. This issue will be revisited later in the tutorial when a PWM scheme will be implemented.

WARNI NG: Thi s message i s f r oma smal l t i me- st ep
VSC component of t ype: ph3l ev2
and of component name: BRDG1
l ocat ed on t he f i r st pr ocessor
of a VSC br i dge named: VB1
i n subsyst emnumber : 1.
The f i r i ng pul se wor d i nput "FPWORD1" f or t he VSC
component i s not l ocal l y pr oduced on t he pr ocessor but
comes f r omt he l ar ge t i me- st ep backpl ane.
Consequent l y, f i r i ng pul se wor d i nput
changes onl y once i n a l ar ge t i me- st ep.
The f i r i ng coul d have bet t er r esol ut i on i f
i t was cr eat ed on t he l ocal pr ocessor .
Not ed i n f cn: r net _ph3l ev2_code

War ni ng i ssued f r om<r net _ph3l ev2_code>

Once the case has been successfully compiled, RUNTIME can be launched and the DC and AC side voltage signals
can be plotted. Figure 3.8 shows plots of the results that should be obtained. The signal VP, as expected, is the
maximum value of the signals VA, VB and VC; conversely the signal VN is the minimum amongst them.
Figure 3.7: Change the source of the firing pulse so that it originates from the control compiler
-12-

Figure 3.8: RUNTIME plot of the AC and DC side signals from the voltage rectifier circuit
-13-

ALTENATIVE APPROACHES:
There are a number of alternative approaches to building the diode rectifier in this section; some of these are
briefly described below. Each method has its own distinct advantages and disadvantages.
Discrete Switching Elements:
The small time-step component rtds_vsc_VALVE1 can be used to build the diode bridge. The vtype parameter
can be modified so that several types of switching elements can be represented. Among them are a GTO, a GTO
with an anti-parallel diode, a diode, a thyristor and a thyristor with an anti parallel diode. To build the diode
rectifier of this section each switching element would be a separate component. Using this approach any
arbitrary circuit topology can be implemented and is particularly useful when circuits having non-standard
topology must be simulated. Figure 3.9A shows the implementation of diode rectifier using this approach.
Two Level VSC Bridge:
Certain common circuit topologies have been implemented as single components. The rtds_vsc_PH3LEV2
component, for instance, consists of six GTOs/IGBTs with anti-parallel diodes and is useful for modeling two-level
converters. In this section this component was used to build a diode rectifier by simply not providing any gating
signals to the GTOs/IGBTs. Figure 3.9B shows the implementation of diode rectifier using this approach. There
is essentially no difference in how this circuit functions when compared to the first implementation using discrete
switching elements. There are two advantages of using this model, however, (1) the circuit is more easily
assembled and (2) foreknowledge of the topology allowed the component to be coded in a more efficient manner.
The benefit of these added efficiencies is that the simulation time-step might be reduced or the number of
components that can be simulated might be increased. Another useful topology in the library is a single leg of a
three-level converter, rtds_vsc_PH1LEV3.
Interfaced Six Pulse Bridge:
A third option in assembling the simple diode rectifier is to use the rtds_vsc_LEV2 component. Figure 3.9C shows
the implementation of diode rectifier using this component. This third implementation of the diode rectifier is
fundamentally different from the two previous implementations. The bridge in the rtds_vsc_LEV2 component is
actually interfaced with the small time-step network solution using a transmission line having a wave propagation
delay of one small time-step. The presence of this short t-line implies that what occurs at one end of the
transmission line doesnt affect what occurs at the other end for at least one small time-step. The valve group is
thus effectively decoupled from the small time-step network solution during any single small time-step. This is
the same principle used to divide a large simulation across multiple racks. Instead of modeling the VSC switches
in a network solution using the methods introduced in section 2, an open switch is a small conductance and closed
switch is a large conductance. All possible conductance matrices for the circuit are pre-calculated and stored in
memory; they are then referenced as needed. The anomalous power loses previously described dont occur and
higher switching frequencies can be supported. The disadvantage, of course, is that transmission lines which do
not exist in the real system have to been introduced into the circuit. These transmission lines can lead to
reflections and other effects and thus this component must be applied with care.

-14-

(A)
(C)
(B)
Figure 3.9: Alternative constructions for the diode rectifier circuit using (A) discrete valves, (B) valve bridge and
(C) interfaced valve bridge
-15-

4 SIMPLE STATCOM EXAMPLE

The small time-step capabilities of the RTDS Simulator are often used to model high frequency switching circuits
such as those used in PWM schemes. In this next section the foundations established in the previous section are
built upon and a simple STATCOM will be assembled. A STATCOM controls the flow of reactive power into a bus
and can thus be used to regulate the voltage at that bus. Figure 4.1 gives details about the topology of the circuit
that will be constructed; it consists of an infinite bus feeding a load that can be switched in or out of service by
controlling a breaker. The system side is 93kV while the voltage on the converter side of the transformer is
11.5kV. The base power for the system is 100 MVA. A significant drop in the voltage at the load bus will occur
w hen the load is connected; the purpose of the STATCOM is to correct this voltage drop.

The circuit of Figure 4.1: Overview of the Simplified STATCOM case being assembled. differs from a practical
STATCOM in that ideal voltage sources are used for the DC bus. Normally large capacitors are used on the DC
side of the STATCOM but the use of ideal sources will significantly ease the construction of a control system since
the capacitor voltage will not need to be actively regulated. In a practical STATCOM the concepts of
instantaneous reactive power are deployed in order to achieve fast, sub-cycle control of the bus voltage. Here, a
simplified approach will be adopted where conventionally defined reactive power will be regulated.

x
reactor

r
s
x
s

x
transformer

filter
V
DC

STATCOM
r
l

x
l

v
s

Load
Infinite Bus
P
inj
, Q
inj

V
DC

Figure 4.1: Overview of the Simplified STATCOM case being assembled.
16
STATCOM CIRCUIT:
ThesmalltimestepcircuittobeconstructedisgivenbelowinFigure4.2. Thesystemin93kVonthehighvoltage
side and 11.5kV on the low voltage side; the base MVA is 100. All components must be placed inside a small
timestepbridgebox. Briefdescriptionsofeachoftheimportantpartsofthiscircuitareprovidedbelow.
Figure4.2:DRAFTmodelofSimplifiedSTATCOM
Source:
A controllable source is used to model an infinite bus having a rated voltage of 93 kV LL RMS. The source
impedanceis0.019+j0.064pu(Rs=1.64andXs=5.54 atanominalfrequencyof60Hz). Thecontrolsignals
forthesourceoriginatefromthelargetimestepandthefollowingcircuitcanbeusedtoprovidethesesignals.
Figure4.3:Signalsourceforinfinitebus
Load
Theloadis120MVAwithapowerfactorof0.9322(R
l
=67.25andX
l
=26.11 atanominalfrequencyof60Hz).
The load can be switched in and out of the circuit using the three phase circuit breaker component
rtds_vsc_BKRN3 which is modeled using the same method as other switches in the small timestep. When the
load is switched in, the voltage at Bus 2 is expected to dip and it is this dip that the simplified STATCOM should
regulate.
Filter:
The elements found between Buses 3 and 4 together make up a filter; it consist of reactors and shunt highpass
filter branches. In this tutorial a PWM scheme is used where switching occurs at a frequency of 21 times the
T1PH1
VSC
TRF #1
V1 V2
53.6936 6.3509
MVA =33.33 MVA
TRF #2
V1 V2
53.6936 6.3509
MVA =33.33 MVA
TRF #3
V1 V2
53.6936 6.3509
MVA =33.33 MVA
SRC
1.64 0.0147
+
SRCa
SRCb
SRCc
B
K
R
1
A B C
L
o
a
d
6
7
.2
5
0
.0
6
9
2
5
BKRWORD1
Breaker
7
0
VN3
VN2
VN1
BUS 1 BUS 2
Infinite Bus
H
a
rm
F
ilt1
2
0
0
7
.9
5
1
7
e
-5
0
.6
2
9
5
BUS 3
BRDG1
1
2
3
4
5
6
FLT
0.0006686
VN9
VN8
VN7
BUS 4
VN6
VN5
VN4
Filter
Reactor
Transformer
Switchable
Load
93 kV 11.5 kV
VP
VN
B
R
1
0
.0
0
0
1
+
V
D
C
0
.0
0
0
1
V
D
C
17
fundamental or 1260 Hz. Current and voltage harmonics will be generated in the vicinity of this switching
frequency and the shuntfilter branch will behave as aneffective short circuitat these harmonic frequencies and
effectivelygroundBus3tominimizetheirimpactonthenetwork.
The value for the parameters of the filter are L
reactor
=0.0006686H, R
shunt
= 0.6295, C
shunt
= 200F and L
shunt
=
0.0000795H. TheseparameterchoicesleadtothebodeplotofFigure4.4fortheimpedanceoftheshuntbranch.
Theinputimpedanceoftheshuntbranchis~0.4466at1260Hzwhichissmallrelativetotheimpedanceoffered
by the transformer and reactor at that frequency. At the nominal frequency of 60Hz the input impedance
provided by the shunt filter branch is fairly large and has a value of 13.23 , approximately 10x the base
impedance. Thisimpliesthatthefilterwillhaveaminimalimpactonthecircuitatthenominalfrequency
The size of the reactor was selected almost arbitrarily and the design rules listed below were used to select the
parameters of the shunt highpass filter branches. Justification for the design approach is beyond the scope of
thistutorial.
A) Select the capacitor so that at the nominal frequency of 60Hz, the shunt filter branch behaves like an
open circuit. The impedance of the capacitor can be arbitrarily chosen as 10 pu at 60Hz.

Z
busc
Lv
=
11.5
2
100
= 1.S22 [Eq.4.1]
At the nominal frequency of 60Hz, lct Z
CAP
= 1u pu = 1.S22 1u = 1S.220
C =
1
oz
CAP
=
1
376.99113.22
~2uupF [Eq.4.2]
B) Neglect the parallel resistor and assume a series LC circuit. Using the capacitance calculated in step
(A) select the inductance such that a resonance occurs at the modulation frequency and the impedance
of the capacitor and inductor cancel each other to provide a path to ground. The resonant frequency
of a series LC circuit is =
1
LC
and the resonance should occur at 1260 Hz.
I =
1
o
2
C
=
1
(2n1260)
2
200.65c
-6
= 7.9S17e
-5
E [Eq.4.3]
C) Select R such that its impedance is equal to that of the parallel connected inductance at the modulating
frequency.

R = I = (2n 126u) 7.9S17e
-5
= u.629S2 [Eq.4.4]

Figure4.4:Bodeplotofthemagnitudeoftheshuntbranchimpedance
18
Transformer:
A transformer is typically used to connect the STATCOM and the filters to the bus where voltage regulation is
needed. The impedance is selected as purely reactive and is X
leak
= 0.18 pu (15.568 at 60Hz on the primary
side). The small timestep transformer rtds_vsc_TRFS1PH should be used; it is an ideal transformer. The
threephasetransformershouldbeimplementedusingthreesinglephaseunits,eachratedat33.3MVA.
SixPulseBridge:
Thesixpulsebridgeshownusesthertds_vsc_PH3LEV2component. Thebridgecouldalternatelybeconstructed
using the rtds_vsc_LEV2 component or several rtds_vsc_VALVE1 components as was described earlier in this
tutorial. The firing pulses for these components will be provided by the rtds_vsc_3LGFIR component which will
need to be supported by a rtds_vsc_TRIWAV3 component and a large timestep control system which will be
describedshortly.
DCBus:
TheDCbusfortheSTATCOMwillsimplybeimplementedasanidealsource. Asdiscussedabove,thiswillleadto
simplification of the control system. The source impedance will be selected as purely resistive and as small as
possible. TheDCbusshouldbesetto30kVacrossthepositiveandnegativepoles. (+15kVforthepositivepole
and15kVforthenegativepole)

-19-

STATCOM CONTROLS:
Two regulators are used in this tutorial; the first will control the voltage magnitude at bus 2, the second will
regulate the real power flow. The theoretical basis for our control is derived from Eq. 4.5 and Eq. 4.6. These
two equations describe the physical system that is to be controlled; specifically they describe the real and reactive
power injected into bus 2. The impedance found between bus 2 and bus 3 is assumed to be purely reactive and
is the angle of the voltage at Bus 3 relative to that at Bus 2.
sin [ Eq. 4.5]
2
cos
2
2
[ Eq. 4.6]
Given that there are no capacitor voltages which need to be actively maintained, the power flowing out of the
STATCOM will simply be regulated to zero. This closely approximates a real STATCOM where the real power
consumption is generally quite small. The voltage at bus 2 will be regulated to the nominal value of 1.0 per unit.
It is well documented that the power flowing between buses 2 and 3 is strongly correlated to . Similarly, the
reactive power flow is a strong function of the voltage magnitudes of the buses. Given such strong correlations
will be used to control P
32
and V
3
will be used to control Q
32
. The mutual effects of on Q
32
and of V
3
on P
32
are
effectively ignored but good control should be achievable.
Active Power Regulator:
If is limited to +/- 90 degrees then a simple relationship exist between the electric power transfer, P
inj
, and . If
increases then so will P. Such a relationship is ideally suited for control using the PI controller of Figure 4.5.

Failure to limit the output of the PI controller is a failure to take into account the non-linear nature of the
underlying process and could cause the controller to fail. Consider the case where P
ref
is set to a value above the
theoretical limit of the process,
. The simple PI controller, in an attempt to regulate the power flow, would

cause to increase continually which in turn would cause P
meas
to oscillate.
Figure 4.6 shows the implementation of the Active Power Regulator for this example. As mentioned above, P
ref

will be fixed to zero. The proportional gain is selected as G = 0.01 and the integrator time constant is set to T =
0.1s. These values are selected experimentally and have not been optimized in any way. In order to prevent
windup problems the integrator is reset when the controller is operating in the open loop. For this tutorial, the
controller will only be open looped if firing of the bridges valves is blocked. The integrators are also reset for the
first second after the simulation is started. This was necessary to make certain that the controllers respond
quickly after the simulations start-up electrical transients end. Figure 4.7 shows the integrator reset logic. The
reset logic is not a robust or comprehensive solution but it will work for this example. The same reset logic is
used to reset all the integrators in the STATCOMs controller.

-90
+90

PI
+
-

Pref
Pmeas
Figure 4.5: Block diagram of active power regulator
-20-

Figure 4.6: Implementation of active power regulator

Figure 4.7: Implementation of integrator reset logic
Bus Voltage Regulator:
The objective of the voltage regulator is to regulate the voltage at bus 2 to some pre-defined value. Fortunately
the voltage at bus 2 can be fairly easily regulated by controlling the amount of reactive power injected. If the
reactive power injected into bus 2 increases then so will the voltage at the bus. The PI controller below can be
used to control such a system.

The next step involves determining how to go about controlling the reactive power injecting into bus 2; this will
have to be done indirectly. By inspection of Eq. 4.6, a simple relationship between Q
inj
and V
3
can be found.
Assuming that has been limited to +/- 90 degrees then as V
3
increases, so will Q
inj
. Like before, this simple
relationship is ideally suited to be controlled by a PI controller.

PI
+
-
Q
V2ref
V2meas

PI
+
-
V3
Qref
Qmeas
Figure 4.8: Block diagram of bus 2 voltage regulator
Figure 4.9: Block diagram of reactive power regulator
-21-

The PI regulator above has been designed as though the voltage at bus 3 can be directly controlled. This is in fact
approximately true; the voltage at bus 3 can be controlled by modulation the fixed DC bus voltage. With the
sinusoidal PWM scheme that will be deployed it can be shown that the magnitude of the filtered signal that would
ideally appear at bus 3 will be
. [2] Here V
SRC
is the one half of the fixed DC bus voltage and m
a
is the
PWMs amplitude modulation ratio. Thus the amplitude of the filtered voltage found at bus 3 can be controlled
directly through manipulation of the amplitude modulation ratio.
Cascading the two PI controllers above allows the control of the voltage at bus 2 indirectly by changing the
amplitude modulation ratio. The complete controller is given below in Figure 4.10.

Figure 4.11 shows the implementation of the voltage regulator for this example. Like with the Real Power
Regulator provisions for resetting the integrators during simulation start-up and when operating in the open loop
are included. The first PI controller has a proportional gain of G = 1000 and an integrator time constant of T =
0.0005s. The second PI controller has a proportional gain of G = 0.005 and an integrator time constant of T = 40.
These parameters were also chosen through trial and error. Furthermore, a limiter is added so that the
amplitude modulation ratio is kept in the range of zero and one in order to avoid over-modulation.

Figure 4.11: Implementation of the bus voltage regulator
Signal Filtering:
In order to provide stable results the measured signals used by the voltage regulator and the active power
regulator are first passed through filters; simple real-pole filters are used. The gains for all the filters are set to
one. The time constants for P and Q filters are set to T = 0.2s. The time constant for voltage filter is also set to T
= 0.2s. Again, these parameters are selected heuristically.

PI
+
-
Qref
V2ref
V2meas

PI
+
-
m
Qmeas
Figure 4.10: Complete block diagram of voltage regulator
-22-

Figure 4.12: Regulator input signal measurement and filtering

Sinusoidal Pulse Width Modulation (SPWM):
Two separate regulators have been designed whose outputs define the amplitude and phase of the voltage that
should appear at bus 3 in order to achieve the dual design objectives of regulating the bus 2 voltage and regulating
the active power drawn by the STATCOM. The next step is to generate this desired voltage. Sinusoidal PWM
(SPWM) is used to achieve this objective.
Consider the circuit of Figure 4.13A which shows one leg of the bridge that has been created in this tutorial
example. In a standard SPWM scheme a sinusoidal modulation signal is compared with a high frequency triangle
wave as demonstrated in Figure 4.13B. When the value of the triangle wave exceeds that of the modulation
signal then switch S
1
will be turned on. Conversely, when the amplitude of the triangle wave is less than that of
the modulation waveform then switch S
1
will be turned off. The switch S
2
will be controlled in a complimentary
fashion.

A
-A
V
out

+
-
S
1
S
2
V
DC
V
DC
V
DC
-V
DC
(A)
(B)
(C)
Figure 4.13: Sinusoidal pulse width modulation basic
-23-

The signal V
out
from the circuit will be a switched waveform similar to that shown in Figure 4.13C. It can be
shown that if the amplitudes of the triangle wave and sinusoidal modulation signal are the same then the
amplitude of the fundamental component of V
out
will be equal to the DC rail voltage, V
DC
. Similar principles of
operation apply to all three legs of the bridge.
Modulation Waveforms
The outputs of the active power and bus voltage regulators designed above are and m respectively. Both of
the signals are used in the generation of the modulation waveforms of the PWM scheme that will be deployed.
The control circuit used to generate the modulations signals is shown in Figure 4.14; the frequency is fixed at 60Hz.

Figure 4.14: Control circuit to generate modulation waveforms for sinusoidal PWM

Triangle Waveform
In order to implement SPWM a high frequency triangle wave needs to be compared to the modulation signals.
The small time-step Triangle Wave Generator Component (rtds_vsc_TRIWAV3) will be used to generate this
triangle wave. The triangle wave is generated within the small time-step simulation because a high resolution
signal is needed in order for the switching instants to be calculated with precision.
In practice, the frequency of the triangle wave is commonly an integer multiple of the fundamental frequency.
Since the fundamental frequency can drift in a real system the small time-step triangle wave generator was
designed to accept inputs from a large time-step controls circuit which can track such drift. The circuit of Figure
4.15 is one such circuit that can be quite useful for SPWM applications. A three phase signal can be input into a
PLL whose output is the phase and frequency of that three phase signal. Multiplying the output frequency by the
SPWMs frequency modulation factor, m
f
, yields a frequency signal for a triangle wave. Multiplying the phase
signal by m
f
and fixing it so that is lies between 0 and 2 yields the associated phase signal for the triangle wave.
-24-

Figure 4.15: Generation of support signals for small time-step triangle wave generator

Figure 4.16 further illustrates the generation of the triangle waves phase signal assuming m
f
= 4. The output of
the PLL is multiplied by m
f
= 4 and the result is then fixed so that it lies between the range of 0 and 2. Notice
that result is a phase signal appropriate for a triangle wave having frequency m
f
times that of the original signal.

Figure XX: Generation of the triangle waves phase signal
It was stated earlier that a high resolution triangle wave is needed in order to precisely determine switching
instants. The small time-step component rtds_vsc_TRIWAV3 uses the phase and frequency information
generated by the large time-step control circuit of Figure 4.15 to generate that high resolution triangle wave in the
small time-step. This is done primarily through extrapolation as well as some boundary wrapping. Every small
time-step the incremental phase, , can generally be calculated according to the equation =
0
+ t and based
on the calculated value the proper point on a triangle wave can be fairly easily found using a lookup table and/or
by simple range checking. Figure 4.17 illustrates this concept.
2
2
8
ANGLE
A
TANGLE
t
Figure 4.16: Generation of the triangle waves phase signal
-25-

Some of the default parameters in the rtds_vsc_TRIWAV3 component will need to be changed. The signal label
names assigned to the triangle wave phase and frequency outputs must be specified inside the rtds_vsc_TRIWAV3
component. Only a single triangle wave is needed in this example and its peak-to-peak magnitude will be set to
2.0 with an offset of 0.0; this will produce a triangle wave that oscillates between 1.0. A name must be assigned
to the triangle wave signal that will be output from the component so that it can be referenced by the small
time-step comparator that will be described next. Finally, the triangle wave should explicitly be targeted for
monitoring during RUNTIME so that the performance of the PWM scheme can be evaluated. The user is
encouraged to consult documentation regarding the additional capabilities of the triangle wave generator.

PWM Comparator
At this stage both a triangle wave and the desired modulation signals have been generated. What remains to be
done is a comparison of these signals in order to generate the required firing pulses. This comparison must be
done in the small time-step simulation in order to accurately determine the switching instances. The
rtds_vsc_3LGFIR component is used in order to do the comparison. A single component is capable of doing the
three comparisons needed for the three phase system.
Several inputs must be provided to this component. These include the names of the triangle wave and
modulation signals as well as a de-block signal. The rtds_vsc_3LGFIR component gives the user complete
freedom to specify how the firing pulse word used to control valve firing is generated. Each of the components
three comparators makes one of two possible contributions to the final firing pulse word; one for when its
modulation signal is greater than or equal to the triangle wave and another for when its modulation signal is less
than the triangle wave. The outputs from each of the comparators are then bitwise ORed together. The result
is then ANDed with a de-block signal. The equation for the output of the firing pulse generator is given in Eq. 4.7.
In this equation cmp1t, cmp2b, cmp1t, cmp2b, cmp3t, cmp3b and dblknm are all parameters of the
rtds_vsc_3LGFIR component.
fpout = [(cmp1t || cmp1b) || (cmp2t || cmp2b) || (cmp3t || cmp3b)] && dblknm [ Eq. 4.7]

2
A
-A
2
'
Figure 4.17: Extrapolated ' used to get a value for the triangle wave
-26-

For this tutorial the end objective is to control the valve bridge of the rtds_vsc_PH3LEV2 component. This valve
bridge component is designed in such a fashion that each valve is controlled by a different bit of a firing word
which is referenced as a parameter. Valve 1 is controlled by bit 1, valve 2 by bit 2, valve 3 by bit 3 and so forth.
If the bit associated with any of the valves is one then the valve is conducting, if it is zero then the valve is blocking.
Assume that the bridge receives its firing pulse input word from the rtds_vsc_3LGFIR component and that the
contributions from each of its three comparators are left with their default values which are listed in Table 1.
Each comparator can make one of two possible contributions to the firing pulse word depending on how the
triangle wave and its modulation signal compare. Notice that with the default contributions valves 1 and 2,
valves 3 and 4 and valves 5 and 6 will always be fired in a complementary fashion as needed. The contributions
are also such that comparator 1 affects only bits 1 and 2, comparator 2 affects only bits 3 and 4 and comparator 3
affects only bits 5 and 6. The implication of this is that the contributions from all three comparators can be ORed
together to form a single firing pulse input word without affecting each other. This firing pulse input word is then
ANDed with a de-block signal before being passed to the valve bridge.

Comparator Condition Contribution Contribution

(Decimal) (Binary)

1 Modulation Wave #1 >= Triangle Wave 1 00 00 01

Modulation Wave #1 < Triangle Wave 2 00 00 10



Table 1: Comparator contributions to firing pulse word
Although the component is flexible enough to block only selected valves, for this example all valves are either
blocked or de-blocked. Adding a simple switch that outputs an integer value of 63 when de-blocked (ON state)
and 0 when blocked (OFF state) will achieve the desired objective.

RUNTIME INTERFACE
Create a RUNTIME interface similar to that shown in Figure 4.18. If the STATCOM is blocked then the voltage at
bus 2 should drop significantly when the load is connected. If the STATCOM is de-blocked the voltage at bus 2
should be regulated to around 1pu regardless of whether the load is connected or not.

-27-

Figure 4.18: RUNTIME interface for simple STATCOM example
-28-

Additional Exercise: Change in the DC bus
In the previous case, the DC bus for the STATCOM was implemented as an ideal source. An additional exercise
would be to replace the source with a large capacitor, as this more closely resembles a practical STATCOM.
Figure 4.19 shows the change that needs to be made to the power system. The change can be made by keeping
the same component (rtds_vsc_BRC3) for the DC bus, changing the branch type to RC and excluding the branchs
optional voltage source in the branch. Choose the capacitor value to be 2000F and make the series resistance
0.0001.

Figure 4.19: Bus with capacitors instead of sources

The function of the STATCOM will remain the same, but the addition of the capacitor adds another layer of
complexity to the system. No longer can the power regulator be referenced to zero as real power needs to be
exchanged between the STATCOM and the power system in order to maintain the charge on the capacitors. The
Active Power Regulator developed above will need to be augmented to achieve this objective.

DC Bus Regulator (formerly Active Power Regulator):
The voltage of a capacitor is governed by Eq. 4.8. The voltage seen at the DC bus is determined by the amount
current that can be directed to the bus. This provides a simple relationship between DC Capacitor voltage, V
DC

and P
inj
. To increase V
DC,
inject more active power, and hence current, to the STATCOM. Therefore the DC bus
can be regulated by controlling the real power exchange. The PI controller seen in Figure 4.20 will perform the
required control.

=
1
[ Eq. 4.8]
-29-

As mentioned before, increasing the injected power is done by increasing with the use of a PI controller seen in
By cascading the two PI controllers of Figure 4.5 and 4.20, the DC bus voltage can be regulated indirectly by
changing the load angle,. Figure 4.21 shows the complete block diagram. The reason why the polarity is
reversed for P
ref
and P
meas
, is because injecting P or Q into the power system from the STATCOM is considered the
positive direction while increasing the DC bus voltages, requires power flowing in the negative direction.

dn integrator time constant of 0.25s and a proportional gain of 5 seemed to provide reasonable results.
Figure 4.22 shows the implementation of the DC Bus Regulator. An integrator time constant of 0.25s and a
proportional gain of 5 for the first PI controller seemed to provide reasonable results. The parameters for the
second PI controller are unchanged from earlier in the tutorial.

Figure 4.22: Complete block diagram of DC Bus Regulator

Voltage Regulator:
The voltage regulator will be the same as in the previous cases where the DC bus contained sources.

RUNTIME INTERFACE
Create the same runtime file from the previous case as seen in Figure 4.18. Once again, the voltage at bus 2
should be around 1pu when the STATCOM in deblocked. However, with the addition of the capacitor, the active
and reactive power flowing through network and the STATCOM will be deviate from zero since real power will be
drawn to maintain the capacitor voltage.

PI

+

Pref
Pmeas

PI
+
VDC
VDCref
+90 -
-90
-

PI
+
-
P
VDCref
VDC
Figure 4.20: Block diagram of DC bus regulator
Figure 4.21: Complete block diagram of DC Bus Regulator
30
5 INTERFACING LARGE AND SMALL TIMESTEP SIMULATIONS
Up until this point, all the simulations in this tutorial have consisted entirely of small timestep components.
When possible this is a good option but it isnt always practical. The large timestep library is much more
extensivethanthesmalltimesteplibraryandsometimestheneedforthesemodelsdrivestheneedtointerface
the small andlarge timestep simulations. Also, small timestep simulation is relatively computationally intense
when compared to the large timestep simulation so it doesnt always make sense to model everything with the
levelofdetailprovidedbythesmalltimestepsimulation.
Inordertointerfacethelargeandsmalltimestepsimulationsacomponentcalledaninterfacetransformermust
be used. One side of the interface transformer will have only large timestep components connected to it; the
othersidewillonlybeconnectedtosmalltimestepcomponents.
There are several interface transformers available but the most recent and most stable model is the
rtds_vsc_IRFTRF1component. Currentlythisinterfacetransformerisonlyavailableinsinglephaseform;athree
phase transformer can be created using three of these single phase transformers. Two older interface
transformers include the rtds_vsc_TF3 and the rtds_vsc_STFR4 components. Use of these models, however, is
notrecommendedsincethenewermodelismorestable.
Wheneverpossiblethecircuitshouldbedividedatapointwhereanactualtransformerexists. Thisisduetothe
factthattheinterfacetransformerhasaleakagereactanceandaresistance. Tominimizetheimpactofinserting
theinterfacetransformerintothecircuititisbesttoinsertitapointwherealeakagereactanceandaresistance
already exist. The presence of the leakage and resistance is a consequence of how the transformer is modeled.
Detailsontheimplementationofthertds_vsc_IRFTRF1componentaregivenattheendofthissection.
As an exercise, the simple STATCOM from section 4 can be modified. The transformer will be replaced by an
interfacetransformerandthesourceandloadwillbemodeledusinglargetimestepcomponentssincethereisno
needtomodelthesedeviceswithasmalltimestep. Figure5.1illustrateshowtheoriginalcircuitistobedivided.
T1PH1
VSC
TRF #1
V1 V2
53.6936 6.3509
MVA =33.33MVA
TRF #2
V1 V2
53.6936 6.3509
MVA =33.33MVA
TRF #3
V1 V2
53.6936 6.3509
MVA =33.33MVA
SRC
1.64 0.0147
+
SRCa
SRCb
SRCc
B
K
R
1
A B C
L
o
a
d
6
7
.2
5
0
.0
6
9
2
5
BKRWORD1
Breaker
7
0
VN3
VN2
VN1
BUS 1 BUS 2
Infinite Bus
H
a
rm
F
ilt1
2
0
0
7
.9
5
1
7
e
-5
0
.6
2
9
5
BUS 3
BRDG1
1
2
3
4
5
6
FLT
0.0006686
VN9
VN8
VN7
BUS 4
VN6
VN5
VN4
Filter
Reactor
Transformer
Switchable
Load
93 kV 11.5 kV
VP
VN
B
R
1
0
.0
0
0
1
+
V
D
C
0
.0
0
0
1
V
D
C
MovetoLarget Replacew/InterfaceTR
LeaveinSmall t
Figure5.1:SimulatingasimpleSTATCOMusingtwodifferenttimesteps.
31
The first step would be to remove the source, load and breaker from the small timestep simulation and replace
themwithequivalentlargetimestepcomponents. Thetransformersinthesmalltimestepbridgeboxwillneed
tobereplacedwithinterfacetransformerswithequivalentratings,leakagereactanceandresistance.
The next step is to connect the large time step components to the interface transformer. Fortunately the VSC
bridgeboxbehavessimilartoaconventionalhierarchybox. Ifalargetimesteppowersystemnodeisconnected
to theVSC bridgebox usinga wire then that node canbe duplicated inside the VSCbridgebox and the compiler
willrecognizethatthenodesareinfactthesamenodeandthattheyareelectricallyconnected. Withthenode
duplicated inside the VSC bridge box, it can then easily be connected to the primary side of the interface
transformer. Figure5.2illustrateswhatthecircuitshouldlooklikewiththesourceandloadmodeledinthelarge
timestep. Some signals will need to be monitored and some very minor changes will need to be made to the
controlsystemtogetthingsworkinglikeinsection4.

Infinite Bus
VB1
R R R
L L L
B
R
K
1
A
B
R
K
1
C
B
R
K
1
B
BUS1
N3 N2 N1
1.0 /_ 1.0
BUS 2 93 kV
Switchable
Load
BRK1
Breaker
7
0
BUS 1
src

RRL
RRL
RRL
A
B
C
AC Type
Ell= 93 kV
H
a
rm
F
ilt1
2
0
0
7
.9
5
1
7
e
-5
0
.6
2
9
5
BUS 3
BRDG1
1
2
3
4
5
6
FLT
0.0006686
VN9
VN8
VN7
BUS 4
VN6
VN5
VN4
Filter
Reactor
VP
VN
B
R
1
0
.0
0
0
1
+
V
D
C
0
.0
0
0
1
V
D
C
11.5 kV
BUS1
N3 N2 N1
1.0 /_ 1.0
Transformer
T1
VSC INTERFACE
MAIN
NETWORK
SIDE
SMALL
TIMESTEP
VSC SIDE
V1 V2
53.6936 6.3509
TMVA =33.33MVA
TYPE 2
T2
VSC INTERFACE
MAIN
NETWORK
SIDE
SMALL
TIMESTEP
VSC SIDE
V1 V2
53.6936 6.3509
TMVA =33.33MVA
TYPE 2
T3
VSC INTERFACE
MAIN
NETWORK
SIDE
SMALL
TIMESTEP
VSC SIDE
V1 V2
53.6936 6.3509
TMVA =33.33MVA
TYPE 2
Figure5.2:SimpleSTATCOMcasedividedbetweenlargeandsmalltimestepsimulationfacilities
32
Interface Transformer
The rtds_vsc_IRFTRF1 interface transformer model is implemented as a travelling wave transmission line. This
approachtomodelingthetransformerwaschosenbecauseofthestabilitythatitprovides. Thetransmissionline
iskeptquiteshort;itstravelingtimeisfixedat1.39largetimesteps. Theinductance,L,ofthetransmissionline
ischosensothatitisequaltotheleakageoftheinterfacetransformer. Thecapacitance,C,ofthetransmission
lineisthencalculatedusingthetraveltimeandtheinductanceoftheline. Forthepurposeofthiscalculationthe
lineisassumedtobelossless. Theactualmodelcanaccommodatethepresenceoflosses.
Assumingalosslessline,thetraveltimeofwavepropagatingonatransmissionlineisgivenbyEq.5.1.
tro:cl timc = I C [Eq.5.1]
where ListhelineinductanceinH
CisthelinecapacitanceinF
With the travel time set to 1.39 times the large timestep the Eq. 5.1 can be used to determine the line
capacitance.TheresultisgiveninEq.5.2.
C =
(1.391
lcrgc
)
2
L
[Eq.5.2]
This capacitance is a direct consequence of modeling the transformer as a transmission line and would not
normallyexistinthecircuit. Careshouldbetakentomakecertainthatthiscapacitanceisnttoolarge. Ifitis,
then it will start to impact the simulation, something which should be avoided. In general, the value of X
C
shouldbesignificantlylargerthanthesurroundingimpedances.
ByinspectionofEq.5.2,itisevidentthatiftheleakageoftheinterfacetransformerischosenverysmallthenthe
capacitance,C,willbelarge. Inordertheavoidthissituationtheinterfacetransformerleakagemustbegreater
than0.05pu.
Thecapacitanceandinductancedescribedaboverepresentdistributedparameters. Inordertobeabletoassess
whether the capacitance of the line has become too large it is helpful to find the effective capacitance seen at
terminals of the interface transformer. In order to do this the circuit equivalent for the transmission
line/interfacetransformermustbefound. Figure5.3showsthisequivalent,anidealtransformerhasbeenadded
to the transmission line circuit equivalent to model the voltage transformation capabilities of the interface
transformer.
1 N
Z
c
c
2

2
Small
TimeStep
Simulation
Large
TimeStep
Simulation
Figure5.3: circuitequivalentfortheinterfacetransformerwithidealtransformer
-33-

The effective capacitive reactance of the interface transformer seen from the large time-step side of the interface
transformer is labelled as X
C
and can be calculated using Eq. 5.3. [3] In this equation Z
C
is the characteristic
impedance of the line, is the propagation constant of the line and l is the length of the line.

1
=
1
tanh
1
[ Eq.5.3]

With the assumption of a lossless line Eq. 5.3 can be simplified to Eq. 5.4.

1
=
1
tanh
1.8
1
[ Eq. 5.4]
where

When a case containing an interface transformer is compiled the effective capacitive reactance is calculated for
the rated frequency of the interface transformer and is listed in the MAP file. For convenience, the effective
capacitance of the line is also referred to the small time-step side of the ideal transformer and listed in the MAP
file. An excerpt of the listing is provided below:
VSC component model of t ype "i f ct r f 1"
named: T1
wi t hi n t he BRI DGE named: VB1
i n subsyst em: #1
i s assi gned t o GPC Car d #2 Pr ocessor A

At a t ap f act or of 1. 0, t her e i s an ef f ect i ve
capaci t i ve r eact ance connect ed bet ween t he
pr i mar y t er mi nal s of 2. 704987e+004 Ohms.

Regar dl ess of t he t ap f act or , t her e i s an ef f ect i ve
capaci t i ve r eact ance connect ed bet ween t he
secondar y t er mi nal s of 3. 784344e+002 Ohms.

The MAP file can be viewed by pressing the view button in DRAFTs toolbar and selecting MAP File in the dialog
that appears. Figure 5.4 shows the button that should be pressed.

Figure 5.4: Opening a MAP File

-34-

6 CONNECTING VSC BRIDGE BOXES USING SMALL TIME-STEP
TRANSMISSION LINES

Currently, each VSC bridge box can contain a maximum of 30 nodes and about 32 switching devices. It is
recognized that there is sometimes a need to model larger switching networks. In response to this need, the VSC
CrossCard Bergeron Transmission Line model has been developed. The transmission line model can be used
either to model a transmission line in a single VSC Bridge Box or they can be used to connect two VSC Bridge Boxes
together. It is this latter ability to link bridge boxes that will be the focus of this section.
The process of linking small time-step bridge boxes is analogous to connecting different racks for the large
time-step simulation. The network solutions for each bridge box are effectively decoupled if the travelling time
of the transmission line connected between them is greater than a small time-step. This decoupling allows the
network solutions to be solved independently and results in significant computational savings. Given that a small
time-step is typically 1.5~2.5s and assuming a wave propagation velocity of 3x10
8
m/s the minimum length of the
small time-step transmission line ends up being on the order to 430 to 740m long, significantly shorter than the
large time-step transmission lines which are typically on the order of 15km long.
Hardware Connections:
Large time-step transmission lines are used to communicate from one rack to another. Signal communication is
managed by the GTWIF and in order to communicate from one rack to another there has to be a fibre optic cable
linking the GTWIF cards of the respective racks.
Analogously, small time-step transmission lines are used to communicate from one small time-step bridge box to
another. In order to communicate between the two bridge boxes there must be a fibre optic link between them.
Unlike with large time-step t-lines where racks are linked through the GTWIF cards, small time-step t-lines are
linked through the GPCs card GTCOM ports.
Each GPC card has four fibre optic ports, two are GTCOM ports and two are GTIO ports which are used to connect
IO cards. The topmost port is GTCOM port 3 while the second from the top is GTCOM port 4. Please refer to
Figure 6.1 below for a diagram on how to locate these ports.

Figure 6.1: Location of GTCOM ports on GPC processor card

-35-

As already stated, in order to connect a transmission line between one bridge box and another there must be a
physical fibre optic cable connecting the cards on which the bridges are running. The signals for up to 8
transmission lines can communicate over the same fibre cable and both processors on a GPC card can
simultaneously access the same GTCOM port. Figure 6.2 below shows three different examples of how small
time-step bridge boxes can be linked. The processors on which the bridge boxes are running have been selected
arbitrarily. A line connecting any two bridge boxes in the diagram indicates that one or more tlines span them;
lines of the same color represent the same physical fibre optic cable. The GTCOM ports to which each end of a
fibre is connected are also indicated in the diagram.

Figure 6.2: Sample bridge box Interconnections

Small Time-Step Transmission Lines:
Similar to large time-step transmission lines, three things are needed to make a small time-step transmission line
(1) a sending end terminal, (2) a receiving end terminal and (3) a calculation block. Figure 6.3 below shows the
DRAFT icons for these components. They are linked by the compiler if they share the same T-LINE NAME.

-36-

Figure 6.3: (A) Sending End, (B) Receiving End and (C) Calculation Block for a Small Time-Step T-line

In order to link two bridge boxes one end of the small time-step transmission line would be placed in one of the
bridge boxes and the other end would be placed in the second bridge box; the calculation block can be placed in
either. Figure 6.4 illustrates how a simple circuit might be divided between two bridge boxes. Generally the
process of creating the data for a small time-step T-line is identical to that needed for a large time-step
transmission line. Please review Tutorial Chapter 2: Simple AC System for details on this process.

Figure 6.4: Using a transmission line to connect two VSC bridge boxes

One important difference from large time-step transmission lines is that the GTCOM port used must explicitly be
specified inside each terminal of the transmission line. Figure 6.5 shows the parameter which must be changed
in each of the transmission line terminals.
(C)
(A) (B)
-37-

Figure 6.5: Specification of the GTCOM port inside a transmission line's terminals

When a case which includes small time-step transmission lines is compiled successfully then a .txt file is generated
that is named DRAFTFILENAME_comm_fiber_patching.txt. This file is located in the project directory and lists
where all the necessary fibre connections should be made. This file is especially useful if you have many
connections. The content of such a file is listed below:

Opt i cal f i ber s must be connect ed bet ween
communi cat i on por t s on t he backs of
pr ocessor car ds as f ol l ows:

END No. 1 END No. 2
r ack car d por t <- - - - > r ack car d por t

7 1AB 3 7 1AB 4

Because of the transmission lines dependence on a physical fibre connection it becomes useful to be able to fix
the processor on which the small time-step bridge will run. If this is not done then the processor to which a given
VSC bridge box is assigned can change from one DRAFT compilation to the next. This would require that frequent
changes to the GTCOM fibre connections be made. Not only would this be tedious, it is also error-prone. The
processor to which a specific VSC Bridge is assigned can be manually set by the right-clicking on a given bridge box
and selecting Edit -> Parameters. Figure 6.6 show the parameters that need to be modified in order to manually
assign a bridge box to a specific physical processor.
-38-

Figure 6.6: Parameters associated with manual processor allocation of VSC bridge boxes

-39-

7 SMALL TIME-STEP IO

Importing and exporting signals into and out of the small time-step simulation is fairly straight forward. This
section provides a brief rundown of how to do this for both digital and analog signals.
Analog Outputs
All small time-step analog signals are output from the RTDS simulator on an individual basis. The user must
specifically indicate which signals they want output and where they would like those signals output. This is
typically done directly within individual small time-step components. The signals available to be output will vary
from one component to another. In general a signal can either be output to one of the processing cards
faceplate outputs or to a GTAO card connected to the processor. The process of sending a signal to both of these
targets is described below.
Faceplate AO:
Generally small time-step components will have a tab named either ENABLE FACEPLATE D/A OUTPUT or other
similar name. This tab allows the user to select the signals intended for output through the faceplate analog
outputs. As mentioned, the signals available to be output will vary from one component to another. After a
signal has been selected for output through the faceplate then another tab will be become available. The name
of the tab will vary but it will be something along the lines of FACEPLATE D/A CHANNEL ASSIGNMENT and it will
allow the signal to be assigned to a specific channel. The channel can be any value between 1 and 12. The
signal will be written to the channel of the processor on which the model is running (either processor A or B). A
scaling constant can be used to modify the signal of interest so that it lies within the faceplate analog outputs
dynamic range of +/- 10V. A unique offset can also be added to each of the faceplate outputs. Figure 7.2
highlights the parameters that would have to be changed if a branch current were to be monitored though the
faceplate.

Figure 7.1: Menu items related to front panel analog outputs

-40-

GTAO:
The process of sending a signal the GTAO is similar to that needed to output a signal through the faceplate but a
few additional steps are needed. Every small time-step component must be assigned to a processor and each
processor can access up to two GTAO cards. Each GTAO is referred to as either GTAO1 or GTAO2. The first
step is to enable components within the small time-step bridge box to access the GTAO cards. This is done inside
the properties of the VSC bridge box as shown in Figure 7.2.

Figure 7.2: Enable access to GTAO card inside the VSC bridge box
If analog output through at least one of the GTAOs has been enabled then the menu of Figure 7.3 will appear and
details about the physical connections of the GTAO can be entered. Specifically, the GTAO card number and the
GTIO fiber port number to which it is connected must be entered. It should be noted that only the first two
GTAO cards in any chain can be accessed.

Figure 7.3: Specify GTAO card number and GTIO Fiber port to which it connects

NOTE: Once access to the GTAO cards has been enabled within the small time-step bridge box then signals can
be freely assigned to the GTAO channels within individual components. Failure to complete the above steps
will trigger errors when the case is compiled.
Generally small time-step components will have a tab called ENABLE GTAO D/A OUTPUT or something similar.
This tab allows the user to select the signals intended for output through a GTAO analog output card. Like with
the faceplate analog outputs, the signals which are available to be output will vary from one component to
another. When at least one signal is chosen for output through the GTAO another tab will appear (if not already
visible); in it the user must specify the GTAO card to which the each signal is to be sent. This is done by referring
to the GTAO1 or GTAO2 aliases that are assigned to physical GTAO cards in the small time-step bridge box. The
specific GTAO channel must also be specified; any value between 1 and 12 is valid but if multiple signals are
assigned to the same channel of the same GTAO card then an error will result upon compiling the case. A scaling
-41-

constant must be specified for each channel. The scaling constant is usually chosen so that a scaled signal falls
within the +/- 10V dynamic range GTAO card. Like the faceplate analog outputs, an offset can be added to the
scaled output and the output can be inverted if desired. Figure 7.4 highlights the parameters that would have to
be changed if a branch current were to be monitored through a GTAO.

Figure 7.4: Menu items related to GTAO analog outputs
It is desirable to have the ability to control the processor to which a small time-step bridge box is allocated. This
is especially true when external equipment needs to be interfaced through the small time-step component. In
general the compiler can automatically allocate the bridge box to an available processor but the allocation can
potentially change as a case is developed. This opens up the possibility that a small change in a case could cause
the small time-step bridge box to get bumped to another processor and thus would require all the external
connections to be physically moved. This potential problem can be avoided by manually assigning components
to a processor; the small time-step bridge box will thus always get allocated to the specified processor each time
the case is compiled. Figure 7.5 shows the parameters in the bridge box which allow the user to manually assign
it to a specific processor.

Figure 7.5: Manual processor assignment of small time-step bridge box
-42-

Digital Input
GTDI:
Digital input signals are used extensively in small time-step simulation for things like providing firing pulses to
power electronic switches. The GTDI IO card is required in order to bring digital signals into the small time-step
simulation. A small time-step bridge box can access up to two different GTDI cards but they must be the first two
GTDI cards in the chain.
As with the GTAO, the first step to using the GTDI is to enable components within the small time-step bridge box to
access them. This is done inside the properties of the VSC bridge box as is shown in Figure 7.6.

Figure 7.6: Enable access to GTDI card inside the VSC bridge box
After the digital input from the GTDI card has been enabled then the menu of Figure 7.7 will appear where details
about the physical connections of the GTDI can be entered; the GTDI card number and the GTIO Fiber Port number
to which it is connected must be specified. Also, two signal names to which the inputs read from the GTDI card
can be assigned should be specified. The GTDI has 64 channels; channels 1-32 get assigned to GTDI word 1 and
the channels 33-64 get assigned to GTDI word 2. These words can then be referenced by various small time-step
components.

Figure 7.7: Specify GTDI card number, the GTIO Fiber port, and the signal names for the read signals

-43-

Once access to the GTDI cards has been enabled within the small time-step bridge box and their inputs have been
assigned to signals then these signals can be freely referenced by individual components. Most components that
can accept digital inputs will have a tab called FIRING PULSE INPUT. If the option exists then the source of the
firing pulse input word should be specified as CC_WORD. One of the signal names assigned inside the small
time-step bridge box can then be referenced inside the component. Figure 7.8 illustrates how this can be done
for the three-phase, two-level bridge component (rtds_vsc_PH3LEV2); one of the GTDIs input is presumed to
have been assigned to the control word GTDI1W1 inside the small time-step bridge box.

Figure 7.8: Referencing inputs from a GTDI inside a small time-step component

Analog Input
GTAI:
In order to bring analog signals into the small time-step simulation the rtds_VSC_GTAI component can be used.
The icon for the component is shown in Figure 7.9.

Figure 7.9: Icon for small time-step GTAI component
-44-

This component works in much the same way that the large time step GTAI component works. Details about the
physical connections of the GTAI must be specified; this includes the GTAI card number and the GTIO fiber port
number to which it connects. Each of the GTAIs channels can be enabled individually. A separate scaling
constant and offset can be specified for each channel. The read GTAI signals can also be made available in the
large time-step or through the front panel analog outputs if desired.

Digital Output
GTDO:
In order to output digital signals from the small time-step simulation the rtds_VSC_GTDO component can be used.
The icon for the component is shown in Figure 7.10.

Figure 7.10: Icon for small time-step GTDO component
This component works in much the same way that the large time step GTDO component works. Details about
the physical connections of the GTDO must be specified; this includes the GTDO card number and the GTIO fiber
port number to which it connects. The 64 channels of the GTDO card are divided into four 16 channel banks.
Each bank is controlled by a different control signal and can be enabled or disabled independently. The 16 least
significant bits of the first control signal are assigned to output channels 1-16; the 16 least significant bits of the
second control signal are assigned to output channels 17-32, etc.

-45-

8 SELECTING VALVE PARAMETERS

As discussed in section 2 of this tutorial, several shortcuts are used mimic the behaviour of a switch. An open
circuit is modeled as an RC branch and a short circuit is modeled as an L branch. This approach is selected
primarily because it allows the freedom to select R, L and C in such a fashion that the conductance value for when
the switch is opened, g
oc,
and when it is closed g
sc
are the same. The change in switching state can then be
completely represented by changes in current injections. This significantly simplifies the required calculations
because the matrix inversion of Eq. 2.5 is not required by the network solution.
The validity of the modeling approach used for small time-step simulation is based upon the accuracy with which a
large resistance can be represented by an RC circuit and the accuracy with which a small resistance can be
represented by an inductance. The parameters R, L and C must be selected with care in order to make certain
that the chosen approximations are accurate. In this section the difference constraints which are place on the
selection of these parameters is discussed.
1. The main objective of modeling an open-circuit as a RC circuit and a short circuit as an inductor is to avoid
the need for a matrix inversion whenever a switch changes states. In order to achieve this objective, the
conductance values for both states must be the same. This leads directly to Eq. 8.1, the first constraint
imposed on the selection or R, L and C.

2
= +
2
[ Eq. 8.1]
2. With the chosen modeling approach there is the potential for undesired interactions between the
switches. Consider two series connected switches, one in the ON state and the other in the OFF state.
Using the conventional modeling approach this would be a large resistance in series with small resistance
but using the proposed approach it is actually represented by a series RLC circuit. It is possible that the
response of such a circuit could be poorly damped when subjected to a disturbance. If possible it is
desirable to select R, L and C parameters for the switches such that the response of the circuit to a
disturbance is well damped. The challenge is that switches can be connected in any arbitrary topology
and that the equations relating damping to the parameter choices will change accordingly. A heuristic
approach must therefore be adopted; the values of R, L and C are selected so that good damping is
achieved for series connected switches, one ON and the other OFF. This topology is illustrated in Figure
8.1 and is one that is commonly found in VSC converters.

Figure 8.1: Series connected switches, one ON and the other OFF
R
C
L
v(t)
i(t)
v(t)
i(t)
-46-

Writing the transfer function relating for
()
()
results in a second order function for which it is easy to
define the damping factor, , and natural frequency, w
n
. The transfer function, and
n
are given in
equations 8.2 through 8.4.

()
()
=
2
+
+
1
[ Eq. 8.2]
where 2
[Eq. 8.3]

=
1
[Eq. 8.4]

The desired damping of the circuit is something that will be specified as a valve parameter; the natural
frequency is not so much a concern. Substituting out
n
from Eq. 8.3 and Eq. 8.4 leads to Eq. 8.5, the
second constraint imposed on the selection or R, L and C.
2
1
[Eq. 8.5]
3. As a result of the modeling method there are artificial losses which occur every time a switch changes
states. For slowly switched circuits these loses are not a concern but as the switching frequency
increases theses losses start to accumulate. The aim of the final constraint applied to the selection of R,
L and C is to minimize these losses.

Consider the diagram of Figure 8.3 which shows a comparison of the current established in an ideal switch
at turn-on versus the current established in an inductor, the chosen representation for a switch in the ON
state. Assuming that L will be quite small, when the switch starts to the conduct the current should be
established relatively quickly. This is required if good simulation results are to be achieved. If the valve
will stay in its switching state long enough so that the inductor representing it charges to its full capacity
then the energy stored equals
=
1
2
. When the switch turns off then the energy stored is

lost, because the L branch is abruptly changed to an RC branch.

Valve Current Response (Ideal)
I
conduct
Valve Current Response ( L branch)

t

valve ON

valve OFF

Figure 8.2: Comparison of current establishment in ideal switch and small time-step switch
-47-

Consider the diagram of Figure 8.3 which shows a comparison of the voltage established across an ideal
switch versus the voltage established across the capacitor in an RC circuit. Assuming that the
capacitance will be quite small, when the switch is opened the voltage across the capacitor should be
established fairly quickly. This is required if good simulation results are to be achieved. If the valve
stays in its switching state long enough so that the capacitor representing it charges to its full capacity the
energy stored will be
. When the switch turns on again the energy stored is lost, because
the RC branch will abruptly be changed to an L branch.

The goal is to minimize the total energy lost during a switching cycle. This quantity is given by Eq. 8.6.

=
1
2
2
+

2
[ Eq. 8.6 ]
It can be shown that this is achieved when the Eq. 8.7 is satisfied. This is the last of the 3 equations that
are used to constrain the selection of R, L and C in the chosen valve representation.

2
=
1
2
2
[ Eq. 8.7 ]
Equations 8.1, 8.5 and 8.7 can be solved for the parameters R, L and C. The results are given in Equations 8.8
through 8.10.
= 2 +
2
+ 1
t
2
[ Eq. 8.8 ]
= +
2
+ 1
t
2
2
1
[ Eq. 8.9 ]
=
2
2
[ Eq. 8.10 ]
The parameters t, , v
block
and i
conduct
are all assumed to be known. The small time-step size is calculated during
the compile. The damping, blocked voltage during switching and conduction current during switching are all user
specifiable parameters. Components that model switches using the method described above will generally have
a properties tab labelled VALVE PARAMETERS. Figure 8.4 shows such a tab for the rtds_vsc_PH3LEV2
component.
Valve Voltage Response (Ideal)
V
block
Valve Voltage Response (RC branch)

t

valve OFF

valve ON

Figure 8.3: Comparison of voltage established across an ideal switch and the capacitance in an RC circuit
-48-

Figure 8.4: Properties tab where valve parameters are specified
After solving for R, L and C it is possible to write equations for X
C
and X
L
as a function of frequency. These
equations are given in Eq. 8.11 and Eq. 8.12.
= 2 2 +
2
+1
t
2
[ Eq. 8.11 ]
=
2
2+
2
+1
t
2

[ Eq. 8.12 ]
Given that the damping factor, , is limited to lie between 0.7 and 1.33 and that the time-step, t, will generally
be on the order of 2s. Assuming that ~ 1 and t ~ 2s Eq. 8.11 and Eq. 8.12 above are approximately
equal to Eq. 8.13 and Eq. 8.14 below.

1 10
5
[ Eq. 8.13 ]

110
5
[ Eq. 8.14 ]
By inspection up to about 10kHz X
L
is at most about 0.1
and X
C
is at least 10
. If the ratio

is selected as the base impedance then a short will be a relatively small impedance and an open circuit will be a
relatively large impedance.

Strategy for Selecting Vbl ock and I conduct
Quite often the default values for v
block
and i
conduct
are reasonable and do not need to be changed. If there is,
however, some concern about whether the switch is approximating an open circuit when OFF and a closed circuit
when ON then the ratio of v
block
and i
conduct
can be changed so that it is approximately equal to the base impedance
of the system. In cases where abnormally high losses are observed, the values of v
block
and i
conduct
can be adjusted
so that they more accurately represent the average blocked voltage and the average conducted current seen by
the switch. A balance must be struck between (1) having the switch represent a large impedance when off/ small
impedance when on and (2) avoiding excessive losses which are anomalies of the modeling approach.
-49-

9 DISTRIBUTING PROCESSING LOAD OVER TWO PROCESSORS

The method used for modeling a switch in small time-step simulations begins to lose its accuracy as the time-step
increases. It is therefore desirable to keep the time-step small, preferably below 2.5s. The time-step used is a
function of the complexity of the small time-step circuit; as the number of components inside a VSC bridge box
grows the time-step will increase. An estimate of the small time-step is calculated when the case is compiled and
the calculated value is written to the MAP file. Inside the MAP file a section similar to the one listed below shows
the small time-step that is used.

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
RI SC- based VSC_NET1 Br i dge model named: VB1
i n subsyst em: #1
i s assi gned t o GPC Car d #1 Pr ocessor B

The Br i dge model has 28 smal l
t i me- st eps i n each l ar ge t i me- st ep.

The smal l t i me- st ep si ze i s 1. 785714 mi cr oseconds.

The cal cul at i on t i me per mi t t ed f or each
smal l t i me- st ep i s 1724 nanoseconds.

Ther e i s no T0 out put . I f t her e had been
i t woul d have gone out i n smal l st ep number : 2.
Any T2 out put i s schedul ed f or smal l st ep number : 14.

The smal l - st ep cl ock count on pr ocessor A
i s expect ed t o be 1309 cl ocks wi t hout t he mar gi n.
The User speci f i ed mar gi n i s 360 nanoseconds ( 360 cl ocks ) .

The VSC net wor k sol ut i on met hod on 1st pr ocessor
i s W- mat r i x.
Est i mat ed W- mat r i x = 246 cl ocks.
Est i mat ed Gi - mat r i x = 434 cl ocks.

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

If the time-step becomes large then it is advisable to distribute the calculation load over two processors in order to
reduce it. As a general guideline, if a small time-step circuit has more than 18 single-phase switches or if several
computation-heavy components (ie: small time-step machine model) are used then it is a good idea to use two
processors. If the small time-step is larger than 3s then a warning will be issued, this signals to the user that the
processing load should be re-distributed.
By default the small time-step bridge box taken from the library will run on a single processor. In order to use
two processors for the calculation of the small time-step simulation the parameter rqnmp inside the VSC bridge
box must be changed to Two. This is shown in Figure 9.1.
-50-

Figure 9.1: Running small time-step simulation on two processors

After two processors have been requested in the bridge boxs properties menu then individual components must
be allocated to either processor one or processor two. Most of the small time-step components will have a
parameter called prc12; this parameter can be assigned a value of either one or two and allows for the allocation
of a component to a particular processor when two processors have been requested by a bridge box. If only one
processor has been requested then all components will be placed on that processor. Figure 9.2 highlights the
prc12 parameter.

Figure 9.2: The prc12 parameter used to assign small time-step components to a particular processor

-51-

10 REFERENCES

[1] T. Maguire and J. Giesbrecht. Small Time-step (<2 Sec) VSC Model for Real Time Digital Simulator.
International Conference on Power System Transients (IPST05). Montreal, Canada. June 19-23, 2005.
[2] Mohan, Undeland, and Robbins. Power Electronics: Converters, Applications, and Design. 2
nd
Ed. Toronto: John
Wiley & Sons, Inc , 1995
[3] Prabha Kundur. Power System Stability and Control. Toronto. McGraw-Hill, Inc. 1994

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Small Time-Step Simulation

sin [ Eq. 4.5]

. The simple PI controller, in an attempt to regulate the power flow, would

5 INTERFACING LARGE AND SMALL TIMESTEP SIMULATIONS

. When the switch turns off then the energy stored is

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