High Step-up Ratio DC-DC Converter Topologies

Part II
Speaker: G. Spiazzi
P. Tenti, L. Rossetto, G. Spiazzi, S. Buso, P. Mattavelli, L. Corradini Dept. of Information Engineering DEI University of Padova

Seminar Outline
Why we need high step-up ratio converters?
Application fields

Low power high step-up ratio topologies

Coupled inductors

High power high step-up ratio topologies

Non isolated Isolated

Cascaded Boost Converter

i1 Ug S1 L1 D1 U1 i2 C1 L2 D2 Io S2 C2 U Ro o

Voltage conversion ratio: M =

Uo Uo U1 1 1 = = Ug U1 Ug 1 d1 1 d2

Reduced S1 and D1 voltage stress High flexibility Suitable for high power applications through interleaving connections Total power processed twice High S2 and D2 voltage stress
3

Boost with Voltage Multiplier Cells

i1 Ug L1 ir Lr u2 Cm2 S Dm1 D u1 C m2 m1 D Io Co U Ro o

Voltage conversion ratio:

Voltage multiplier cell

Uo 2 M= Ug 1 d

Reduced switch and diode voltage stress (UDS Uo/2) ZCS and soft diode turn off through the use of a resonant inductor Lr Suitable for high power applications through interleaving connections Maximum and minimum duty-cycle limitation to guarantee soft commutations High switch RMS current Voltage stress reduction related to the number of cells
4

Boost with Voltage Multiplier Cells

i1 Ug L1 D Io S Co U Ro o

Voltage multiplier cell #1

Voltage multiplier cell #2

Voltage multiplier cell #M

Voltage conversion ratio:

Uo M + 1 M= Ug 1 d

Switch voltage stress:

UDS

Uo M+1
5

Converter Operation (CCM)

iL iD1 iD2

ir
t0 t1 t2 t3 t4 t5
i1 L1 D Io Co U Ro o

T01 = t1-t0

Ug

Converter Operation (CCM)

iL iD1 iD2 ir

t0

t1

t2

t3 t4

t5
i1 L1

ir

Lr

u2 Cm2 D Io Co U Ro o

T12 = t2-t1

Ug

Dm1

u1 C m1

Converter Operation (CCM)

iL iD1 iD2

Soft Dm1 turn off

ir
t0 t1 t2 t3 t4 t5
i1 L1

ir

Lr

u2 Cm2 D Io Co U Ro o

T23 = t3-t2

Ug

Converter Operation (CCM)

iL iD1 iD2

Soft D turn off

ir
t0 t1 t2 t3 t4 t5
i1 L1

ir

Lr

u2 Cm2 D Io Co U Ro o

T34 = t4-t3

Ug

Converter Operation (CCM)

iL iD1 iD2

Soft Dm2 turn off

ir
t0 t1 t2 t3 t4 t5
i1 L1

ir

Lr

u2 Cm2 D Io Co U Ro o

T45 = t5-t4

Ug

D u1 C m2 m1

10

Dual Boost Converter

i1 L1 D1 U1 Io C1 Uo U2 D2 Ro S1 Ug Ig

i2 L2

S2

C2

Voltage conversion ratio: Output voltage of each converter:

M=

Uo 1 + d = Ug 1 d

M1 =

U1 U 1 = M2 = 2 = Ug Ug 1 d

11

Dual Boost Converter

i1 L1

Reduced switch and diode voltage stresses Inductor L1 and L2 rated roughly at U half of total input current Suitable for high power applications through interleaving connections of each module Need for isolated gate driver Floating load connection Limited switch voltage stress reduction Penalty in the converter efficiency (negligible for high conversion ratios)

D1 U1 Io C1 Uo U2 D2 Ro

S1 Ig

i2 L2

S2

C2

12

Dual Boost Converter

i1 L1 D1 U1 Io C1 Uo U2 D2 Ro

Power processed by each module:

P1 = U1Io = P2 = U2Io = P

S1 Ug Ig

Efficiency of each module:

C2

i2 L2

S2

1 =

P1 P1 = Pg P1 + Pd

(U1 + U2 Ug )Io 2P UgIo Po Po T = = = = Pg Po + 2Pd (U1 + U2 Ug )Io + 2Pd 2(P + Pd ) UgIo

1 2M1 1 M 1M 2M1 T = = = = 1 1 2M1 M+1 1 1 M + 1 1 1 2M1 1 1 1
13

Efficiency reduction:

Dual Boost Converter

Efficiency reduction:
0.95

1M T = M + 1 1

Overall efficiency T

0.94 0.93 0.92 0.91 0.9 0.89

1 = 0.95

1 = 0.94 1 = 0.93

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Voltage conversion ratio M

14

Interleaved Boost with Voltage Multiplier

Io D1 D4 C1 L1 S1 i1 Ug L2 i2 S2 D3 D2 Uo Ro

U1 = U2 =

Uo 2

u1

u2

C2

Voltage conversion ratio d > 0.5:

Uo 2 M= = Ug 1 d

Reduced switch and diode voltage stress (Uo/2) Inductor L1 and L2 rated at half of total input current Reduced input current ripple due to interleaved operation Voltage multiplier cell operation requires d > dmin More ringing on switch voltage due to capacitor ESL
15

Current Waveforms d > 0.5

S2 S1 i1 i2

U1 = U2 =

Uo 2
iD3
Io

iD4 iD1 iD2

D1

D4 C1 L1 L2

D3

D2

Uo Ro

u1

u2

C2

S1

i1 Ug

i2 S2

16

Interleaved Boost with Voltage Multiplier

Ug = 20V, Pg = 1280W, Uo = 400V, Po = 1080W

i2 uo uDS2 uDS1
Unbalance due to slightly different switch on times

17

Interleaved Boost with Voltage Multiplier

Ug = 20V, Pg = 1280W, Uo = 400V, Po = 1080W

i1 uo

uDS2

Effect of capacitor ESL and layout parasitic inductances

uDS1

18

Boost with Voltage Doubler

L1 Ug i1 2 S1 D3 u2 D2 Io C2 C
o

Uo Ro

L2

i2

Uo U2 = 2

S2

Voltage conversion ratio d > 0.5:

Uo 2 M= = Ug 1 d

Similar behavior as the interleaved boost with voltage multiplier Problem: for d < 0.5 the switch voltage stress (S1) becomes the output voltage
19

Extension to Higher Step-up Ratios

L1 Ug i1 S1 D1 u2 D2 u3 D3 Io C2 C3 Co Uo Ro

L2

i2

S2

U3 Uo U2 = = 2 3
S3

L3

i3 2

Uo 3 = Voltage conversion ratio d > 2/3: M = Ug 1 d

20

Boost with Voltage Doubler

Interleaved boost with voltage multiplier versus Boost with voltage doubler
Io D1 D4 C1 L1 S1 i1 Ug L2 i2 S2 D3 D2 Co Uo Ro Ug u2 C2 L2 i2 S2 i1 L1 S1 D3 u2 D2 Io C2 C
o

Uo Ro

u1

Similar behavior for duty-cycle higher than 50% but the structure becomes asymmetric
21

Boost with Three-state Switching Cell

D3 D2 Np ig L1 Ug Np S1 S2 D1 Dp is Ns u3 u2 C3 Io C2 Uo Ro C1

u1

Voltage conversion ratio (d > 0.5): Uo n + 1 1 M= = Ug n 1 d

n= Np Ns

Reduced switch and diode voltage stress (depending on n) Reduced input current ripple due to interleaved operation Voltage multiplier cell operation requires d > dmin Correct operation requires L > Lmin Operation modes with very low gain
22

Boost with Three-state Switching Cell

Voltage conversion ratio

u2 = u3 0 DCM operation with very low gain

23

Interleaved Boost with Coupled Inductors and Voltage Multiplier

D1 ns im1 Lm i1 Ld ig Ug i2 Ld np im2 Lm S1 S2 D4 C3 U3 np D3 D2 is C1 ns C2 U2 Uo Ro U1 Io

Voltage conversion ratio d > dmin (CCM):

Uo n + 2 1 M= Ug n 1 d

n=

Np Ns

Lm 1 Lm + L d

Normalized switch voltage stress:

UswN

Usw U3 n = = Uo Uo n + 2
24

Interleaved Boost with Coupled Inductors and Voltage Multiplier

D1 ns im1 Lm i1 Ld ig Ug i2 Ld np im2 Lm S1 S2 D4 C3 U3 np D3 D2 is C1 ns C2 U2 Uo Ro U1 Io

Voltage conversion ratio d > dmin (CCM):

Uo n + 2 1 M= Ug n 1 d

n=

Np Ns

Lm 1 Lm + L d

Reduced switch and diode voltage stress (depending on n) Reduced input current ripple due to interleaved operation No reverse recovery losses (ZCS turn on) Voltage multiplier cell operation requires d > dmin High switch current stress
25

Operation for d > dmin (CCM)

i2 i1

im1 im2

D1 ns im1 Lm i1 Ld D2

is

C1 ns

U1 Io

C2 U2 Uo Ro D3

t0

t1

t2

t3

t4

t5

t6
ig Ug

t7 t8
Ld i2

np

np im2 Lm S1 S2

T01 = t1-t0

D4

C3 U3

26

Operation for d > dmin (CCM)

i2

Soft D3 turn off

im2 im1
D1 C1 ns C2 U2 Uo Ro D3 np im2 Lm S1 S2 D4 U1 Io

i1
im1 Lm i1 Ld np

ns D2

is

t0

t1

t2

t3

t4

t5

t6
ig Ug

t7 t8
Ld i2

T12 = t2-t1

C3 U3

27

Operation for d > dmin (CCM)

i2 i1

S1 ZC turn on

im2 im1
D1 ns im1 Lm D2 is C1 ns C2 U2 Uo Ro D3 np im2 Lm S1 S2 D4 U1 Io

t0

t1

t2

t3

t4

t5

t6
ig Ug

t7 t8
i2

i1 Ld Ld

np

T23 = t3-t2

C3 U3

28

Operation for d > dmin (CCM)

Soft D1 turn off
i2 i1

im2 im1
D1 ns im1 Lm D2 is C1 ns C2 U2 Uo Ro D3 np im2 Lm S1 S2 D4 U1 Io

t0

t1

t2

t3

t4

t5

t6
ig

t7 t8

i1 Ld Ld i2

np

T34 = t4-t3

Ug

C3 U3

29

Operation for d > dmin (CCM)

i2 im2 im1 i1

D1 ns im1 Lm i1 Ld D2

is

C1 ns

U1 Io

C2 U2 Uo Ro D3

t0

t1

t2

t3

t4

t5

t6
ig Ug

t7 t8
Ld i2

np

np im2 Lm S1 S2

T45 = t5-t4

D4

C3 U3

30

Operation for d > dmin (CCM)

i1

Soft D4 turn off

im2 im1
D1 C1 ns C2 U2 Uo Ro D3 np im2 Lm S1 S2 D4 U1 Io

i2
im1 Lm i1 Ld Ld i2

ns D2

is

t0

t1

t2

t3

t4

t5

t6
ig Ug

t7 t8

np

T56 = t6-t5

C3 U3

31

Operation for d > dmin (CCM)

i1

im1
D1 ns im1 Lm i1 Ld ig Ug i2 Ld np im2 Lm S1 S2 D4 C3 U3 np D3 D2

im2
is C1 ns C2 U2 U1 Io

i2
Uo Ro

t0

t1

t2

t3

t4

t5

t6

t7 t8

T67 = t7-t6
32

Operation for d > dmin (CCM)

S2 ZC turn on
i2 i1

im2 im1
D1 ns im1 Lm i1 Ld ig Ug i2 Ld np im2 Lm S1 S2 D4 C3 U3 np D3 D2 is C1 ns C2 U2 U1 Io

t0

Uo Ro

t1

t2

t3

t4

t5

t6

t7 t8

T78 = t8-t7
33

Operation for d < dmin (CCM)

i1 i2

Voltage conversion ratio d < dmin (CCM):

Uo 1 M= Ug 1 2d n= Np Ns
Lm 1 Lm + L d

Im1=im2

The multiplier cell is disabled (u1 = u2 0, U3 Uo) The switch voltage stress becomes equal to the output voltage The magnetizing currents are in phase
34

Voltage Conversion Ratio (CCM)

M
35 30 25

1 n+2 1 = 1 2dmin 2 1 dmin

n = 0.5
20 15 10 5 0 0 dmin 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

dmin
Disabled multiplier cell n = 0.7 n=1

2 = n+4

duty-cycle
35

Minimum Switch Voltage Stress

Normalized switch voltage stress for d = dmin: Normalized switch voltage stress at nominal conditions (d > dmin): Optimum turns ratio:
Usw1N 1 Usw 1 = Uo 1 2dmin M n+4 = nM
Usw n = Uo 2 + n

Usw 2N

Usw1N = Usw 2N

nopt

3 8 = 1 + 1 + (M 1) M 1 9
36

Minimum Switch Voltage Stress

UswNmin
0.5

0.45

0.4

0.35

0.3

0.25 5

11

13

15

17

19

21

23

25
37

Isolated Interleaved High Gain Converter

Active clamp Voltage multiplier
UCL im1 Lm i1 Ld ig Ug i2 Ld np im2 Lm S1 S2 D2 np CCL S3 S4 D1 ns is U1 ns U2 C1 Uo C2 Io Ro

Reduced switch and diode voltage stress Reduced input current ripple due to interleaved operation No reverse recovery losses (ZVS-ZCS switch turn on) Same operation mode independent of duty-cycle value High switch and winding current RMS value
38

Main Waveforms
i2 im1 im2 i1

im1 Lm i1 Ld np

U1 ns ns U2 S1 S2

C1 Uo C2

Io Ro

t0 t1

t2

t3

t4

t5
ig Ug i2 Ld

t6
np im2 Lm

T01 = t1-t0

39

Main Waveforms
S3 ZV & ZC turn on
i2

im1 im2 i1
i1 Ld UCL im1 Lm CCL S3 D1 is U1 ns U2 S2 C1 Uo C2 Io Ro

t0 t1

t2

t3

t4

t5
ig Ug i2 Ld

t6

np ns np

T12 = t2-t1

im2 Lm

40

Main Waveforms
i2

S1 ZV & ZC turn on (i1 is negative when S3 turns off)

im2

im1

i1
im1 Lm i1 Ld np D1 ns np im2 Lm S1 S2 is U1 ns U2 C1 Uo C2 Io Ro

t0 t1

t2

t3

t4

t5
ig Ug i2 Ld

t6

T23 = t3-t2

41

Main Waveforms
i2 i1

Soft D1 turn off (no reverse recovery problem)

im2 im1

im1 Lm i1 Ld np

U1 ns ns U2 S1 S2

C1 Uo C2

Io Ro

t0 t1

t2

t3

t4

t5
ig Ug i2 Ld

t6
np im2 Lm

T34 = t4-t3

42

Main Waveforms
S4 ZV & ZC turn on
i1

im2 im1

UCL im1 Lm i1 Ld ig Ug i2 Ld np im2 Lm np

CCL

S4 U1 C1 Io

i2
t0 t1 i s
ns

ns U2

t2

Uo C2

t3
Ro

t4

t5

t6

S1

D2

T45 = t5-t4
43

Main Waveforms
S2 ZV & ZC turn on (i2 is negative when S4 turns off)
i1

im1 im2

im1 Lm i1 Ld ig Ug i2 Ld np im2 Lm S1 S2 D2 np

i2
U1 C1 Io

t0 t1 i s
ns

ns U2

t2

Uo C2

t3
Ro

t4

t5

t6

T56 = t6-t5
44

Main Waveforms
i2 i1

Soft D2 turn off (no reverse recovery problem)

im1

im2

t0 t1

t2

t3

t4

t5

t6

T01 = t1-t2
45

Mismatch Sensitivity
In case of parameter and/or duty-cycle mismatch between the interleaved boost sections severe current mismatch occurs. The solution is to employ individual clamp capacitors for each subsection (in this case, the mismatch is absorbed by a small difference between the clamp capacitor voltages)
Individual clamp capacitors
CCL1 UCL1 im1 Lm i1 Ld ig Ug i2 Ld np im2 Lm S1 S2 D2
46

CCL2 S3 S4 UCL2 D1 ns is U1 ns U2 C1 Uo C2 Io Ro

np

Isolated Interleaved High Gain Resonant Converter

UCL im1 Lm i1 Ld ig Ug i2 Ld np im2 Lm S1 S2 D2 np CCL

Resonant capacitors
S3 S4 D1 ns is U1 ns Co U2 C2 C1 Uo Ro Io

Different operation mode is achieved by reducing the capacitor value of the voltage multiplier cell Half-cycle resonances occur between capacitor C1 and C2 and transformer leakage inductances Ld.
47

Main Waveforms
S1 S2 on on on on off off D1 off on off off off off D2 off off off off on off

Hard S1 and S2 turn on Soft D1 and D2 turn off ZV & ZC turn on of S3 and S4

T01 = t1-t0 T12 = t2-t1 T23 = t3-t2 T34 = t4-t3 T45 = t5-t4 T56 = t6-t5

on off off on on on

i2

i1

im1

im2

t0

t1

t2

t3

t4

t5 t6
48

Preliminary Experimental Results

Ug = 35V, Uo = 360V, Po = 2500W, fsw = 40kHz High voltage ripple on clamp capacitors
u2 is uDS1

Current waveform is half way between non resonant and resonant behaviors

uGS1

49

Conclusions
For high power applications, high step-up converters working with a quite high input current value should have a continuous input current absorption. Interleaved operation at input side helps to reduce the input current ripple as well as to share the total input current between different conversion subsections. A voltage multiplier at the output side avoids the use of dissipative snubbers across the output diodes. Isolated structures operate in the same manner independent of the duty-cycle value (they are better than the non-isolated ones)
50