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Digital System Design

Homework Report

Vittorio Giovara

Part I
This report will explain the implementation details of the homework assignment of the course Digital
System Design. It will adopt a top-down approach, from the global functionaly to the single module

The chosen board for development of the project is a Diligent Pegasus Board, model Xilinx Spartan2

Figure 1: The adopted board.

Integrated Development Environment

The software application used for implementing the project solution is Xilinx ISE WebPACK 9.2i.

Homework Assignment
The handous for this project are to design a synchronous sequential circuit showing on a seven-
segments display the rightmost digit of the matriculation number (4 in this case). Every two seconds
the digit must shift to the left in the next display slot and start over when the last one is reached. It
is possible to duplicate or to divide in half the shift time by pressing BTN1 or BTN0 resplectively.
The following assumption has been made: if a button is kept pressed, it sends its input repeat-
edly every (about) 200ms, continuously updating the time shift, up to a maximum (and minimum)

Part II
General Functionality
The solution was reached by implementing several small VHDL modules and then connect them with
a schematic file. The next picture shows the connection of the implemented circuit.

Figure 2: The schematic view of the solution.

The reset and clock signals are the same for all the modules and there is no commixture of
control/timing signals with data signals. The btn0 and btn1 inputs are connected to the respective
buttons on the board (BTN0 and BTN1).
displayer constantly sends the same number on the digit output and changes the value of
segment only when the input from divisor goes low.
It’s fdivisor that controls the time shift. At start up it sends the control signal tc every two
seconds (active low) and as result displayer moves the digit to the next left slot of the display; when
the last slot is reached the loop goes on from the first. It is possible to modify the time shift by acting
on the button0 and button1 inputs of fdivisor. The time shift is initialezed every time a button is
When the user presses BTN1 or BTN0 to modify the shift time, the input signal is first filtered
by filterer and then sent to fdivsor. This is done in order not to send additional unwanted inputs
due to bounces of the buttons and the speed of the board processor.
The reset signal is connected to the BTN3 of the board. When this button is pressed, every
module is re-initialized and the system correctly restarts.

Part III
Modular View
In this last part of the report every single module used for the solution will be analyzed, providing
a short description, its input and output signals and a more detailed description of the operations it

- displayer module
This module is the handler for showing digits on the display.

Input Output
clock digit(6:0)
reset segment(3:0)

At reset time the digit signal is initialized to the given number, the segment to the rightmost slot
and the status flag to zero. Then every time the divisor becomes active low, the segment and the
status is updated (according to the previous status flag) for moving the digit in the next left slot.
digit and segment are encoded accordingly to the reference manual of the board.

- fdivisor module
This module sends the control signal for moving the digit at the right time.

Input Output
clock tc

By counting the number of the clock strobes, it is possibile to activate a function only at a selected
time. fdivisor sends a tc signal (active low) when its counter has reached a certain.value (stored
in freq), and is silent in all the other cases. The initial value of freq is 100000000, corresponding to
the necessary number of clock strobes for making the shift time of exactly 2 seconds, since the clock
speed of the board is 50 MHz.
When receiving inputs on button0 or button1 the procedure for doubling or dividing the time shift
is activated; the operation is simply to adjust the value saved in freq with a division or a multiplication
by 2 and to reset the counter value to 0. In order to prevent overflow problems the allowed interval
for freq is limited.
If both buttons are pressed at the same time, button0 has priority over button1.

- filterer module
This module prevents spourious signals to be sent to the other modules when a button is pressed.

Input Output
clock exi

On the first input on ent, the exi output is activated, a flag variable is set to 1 and a timer is initialized
to zero; until the timer reaches a certain value (in this case, 12000000 clock cycles, corresponding to
about 200 ms), every other input on ent is rejected and ext is deactivated.
In this way when the button is pressed, the shift speed is increased (or descreased) only once for
each single pressure, and the system doesn’t suffer from the bounces of the buttons.