T5120 and T5220 TTT

1
Sun SPARC Enterprise

T5120 and T5220
Rack Server TTT
Peter A. Wilson
Technical Marketing
Sun Microsystems, Inc.
Sun Internal and Approved Partners Only 2
Agenda
Introduction
Overview of UltraSPARC T2
Sun SPARC Enterprise T52! servers
> Co"parison to Sun #ire T1!!!$T2!!!
> Syste" Arc%itecture and Tours
> &e"ory' (etwor)in* and IO Epansion
> +is)s' #ans and Power Supplies
> Solaris for T52!
I,O& 2-!
,+O&s for T52!
CRUs$#RUs and Confi*uration Options
Tunin* and Perfor"ance
Tools' Infor"ation and References
. / A ---
CMT Processor Strategy
#irst True Syste" on a C%ip
Scalin* perfor"ance wit% fre1uency is
a dead2end
&ulti2core$&ulti2t%read processors can
eploit application parallelis"
A3le to A**ressively attac) "e"ory
latency
Provide ric% availa3ility feature set
Inte*rate networ)in*' I$O and security
capa3ility
4irtuali5e t%e arc%itecture
Agenda
Introduction
> Co"parison to Sun #ire T1!!!$T2!!!
> Solaris for T52!
I,O& 2-!
,+O&s for T52!
. / A ---
UltraSPARC T2
TrueSyste! "n a C#ip
Up to 7 cores 81-29:5 or 1-69:5
Up to ;6 t%reads per CPU
Up to 1; #<2+I&&s' 6 "e"ory
controllers
> Up to ;69< "e"ory =69< +I&&s>
> 2-5 "e"ory <? of UltraSPARC T1
7 fully pipelined #loatin* Point
units $ core' 1 per core
+ual 1!93it Et%ernet and PCI2E
inte*rated onto c%ip
6&< ,2 =7 3an)s> 1; way
associative
En%anced &AU$Security co2
processor per core
> +ES' 0+ES' AES' RC6' S:A1'
S:A25;' &+5' RSA to 2!67 )ey'
ECC'CRC02
Advanced Power savin* features
;5n" process tec%nolo*y
7 82-59:5
69<ytes$s 3i2directional
#ull Cross <ar
C0 C1 C2 C3 C4 C5 C6 C7
FPU FPU FPU FPU FPU FPU FPU FPU
L2$ L2$ L2$ L2$ L2$ L2$ L2$ L2$
FB DIMM FB DIMM FB DIMM FB DIMM
FB DIMM FB DIMM FB DIMM FB DIMM
PCI-E
NIU
(E-net+)
Sys IF
B!""e# S$%t&' C(#e
2 1!9E Et%ernet
P($e# )*5+
,1-5+t'#e./
MCU MCU MCU MCU
M0U M0U M0U M0U M0U M0U M0U M0U
+&A Su32Syste"
Sun Internal and Approved Partners Only ;
UltraSPARC T2 Processor
L2 Data
Bank 0
SPARC
Core 0
SPARC
Core 1
SPARC
Core 5
SPARC
Core 4
L2 Data
Bank 1
L2 Data
Bank 4
L2 Data
Bank 5
L2 Data
Bank 7
L2 Data
Bank 6
L2 Data
Bank 3
L2 Data
Bank 2
L2B0
L2B1
L2B2
L2B3
L2B5
L2B4
L2B6
L2B7
SPARC
Core 2
SPARC
Core 3
SPARC
Core 7
L2
TAG2
L2
TAG3
L2
TAG7
L2
TAG6
L2
TAG0
L2
TAG1
L2
TAG5
L2
TAG4
MCU0
MCU1
MCU2
MCU3
DMU
PEU
RTX
RDP TDS
CCX
S
I
I
S
I
O
CCU
N
C
U
E
F
U
SPARC
Core 6
MAC
FS1
FS1
FS1
PS1 ES1
#or a video tour wit% Ric) :et%erin*ton' *o to %ttp@$$www-youtu3e-co"$watc%AvB<7+(eCcsa6
Sun Internal and Approved Partners Only D
UltraSPARC T2 Core $lock %iagra!
EXU
I!U
"SU
SPU
T"U
MMU#
$WTW
!%U
%asket
&'ar#"(
EXU)
I!U * Instruction !etch Unit
> + ,- I., /(- lines, 012ay SA
> +31entry 4ully1associati5e IT"-
EXU)# * Integer E&ecution Units
> 3 threa6s share each unit
> E&ecutes one integer
instruction#cycle
"SU * "oa6#Store Unit
> 0,- 7., +- lines, 312ay SA
> (01entry 4ully1associati5e
7T"-
!%U * !loating#%ra8hics Unit
SPU * Stream Processing Unit
> 9ry8togra8hic acceleration
T"U * Tra8 "ogic Unit
> U86ates machine state, han6les
e&ce8tions an6 interru8ts
MMU * Memory Management Unit
> $ar62are ta'le2alk :$WTW;
> 0,-, +3,-, 3M-, (<+M- 8ages
Data
Each 9ore has its o2n !loating Point Unit. This remo5es
com8letely the (= !P restriction o4 T.
>nly a + cycle 8enalty to the !PU
!ully18i8eline6 :e&ce8t 6i5i6e#s?rt;
> 7i5i6e#s?rt in 8arallel 2ith a66 or multi8ly o8erations o4
other threa6s
!ull @IS (.) im8lementation
!PU 8er4orms integer multi8ly, 6i5i6e, 8o8ulation count
Multi8lier enhancements 4or mo6ular arithmetic o8erations
in the 9ry8to Unit
Per4ormance is im8ressi5e...testing an6 tuning still
ha88ening
&loating Point Unit
Sun Internal and Approved Partners Only E
'iagara 2 Crypto Per(or!ance
Data
8
8
1
-
-
-
16
16
16
64
64
64
4
2 rounds/cycle
2 rounds/cycle
3 overlapped cycles
4 words into 44 words
2 column over two cycles
2 cycles per step
2 cycles per step
2 cycles per step
32 bits per cycle
16 rounds
48 rounds
1
-
-
-
10 rounds
12 rounds
14 rounds
80 steps
64 steps
64 steps
1

8/9
25/24
3!683
32
3!
41
30/30
36/36
42/42
160/160
128/128
128/128
1
12"0
4"0
12"0
-
-
-
6"36
5"28
4"56
4"80
6"00
6"00
48"00
Co!!ent
)terations*
$lock
$lock
+,ytes-
Cycles*
$lock

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T
2
Supports ten "ost co""on cip%ers and
secure %as%in* functions
> RC6' +ES' 0+ES' AES2127' AES!1E2' AES225;' &+S' S:A21'
S:A225;
On2c%ip crypto accelerators and 3uilt2in 1!93E vs-
accelerator cards
> F0;G crypto perfor"ance
> H20G CPU over%ead
,eadin* crypto*rap%y perfor"ance
> Over 0! *reater RSA1!26 perfor"ance t%an 22soc)et I<& p51!
<est SS, Perfor"ance
> 2-2 3etter perfor"ace$watt t%an 62soc)et :P +,57592
>
1-D6 3etter perfor"ance$watt t%an 22soc)et :P +,07!95
> 15-; 3etter AES127 perfor"ance t%an crypto acclerator card
Sun Internal and Approved Partners Only 1!
Data
&$0%)MM Me!ory )nter(ace
Fe.t!#e U2t#.SP01C 31 U2t#.SP01C 32
1e4!%#e P%ns 1000 440
05.%2.62e B.n/$%/t' 237Bytesse&(n/ 5076ytesse&(n/
Me8(#y C.9.&%ty !9 t( 16: DIMM s2(ts
Me8(#y C(nt#(22e#s 4 4
DIMMSC'.nne2C(nt#(22e# 020204 0;0204
Me8(#y L.ten&y *6ns 126ns
DIMM s9ee/s 400M<= 667M<=
DIMM P($e# 7$.ttsDIMM 12-5+.ttsDIMM
U9 t( 64: DIMM s2(ts
35:20 !ses 16 DIMM s2(ts
Data
10.,E 'et/ork )nter(ace Unit
!ully Integrate6 Aet2ork Inter4ace Unit
> Eliminates P9I1E chi8set latencies
> /)= 'etter 8er4ormance 5s P9I1E AI9
I Mainly through re6uce6 latency
T2o ) %'E 8orts :XAUI;
+ B& an6 + T& 7MA channels 4or 5irtualiCation
Packet classi4ication
> Incoming 4lo2s are classi4ie6 at layer ( ,/ an6 3 an6 8ut
into the B& 7MA 'u44er accor6ing to the classi4ication
rules that matche6 the 4lo2
n&ge 6e5ice 6ri5er, source 'ase share6 2ith Atlas
Per4ormance estimates, testing#tuning ongoing
I
8ort TX#BX D a'out E.3%'8s in each 6irection 2ith a'out
only 3)1<)= 9PU utilisation
I ( 8ort TX#BX D (%'8sTX, 0%'8sBX 2ith F)10)= 9PU
utilisation :still () threa6s a5aila'le 4or a88lication;
Agenda
Introduction
> Co"parison to Sun#ire T1!!!$T2!!!
> Solaris for T52!
I,O& 2-!
,+O&s for T52!
. / A ---
/
Sun Internal >nly
Sun SPARC Enterprise T5120
UltraSPARC T2 Plat(or!
E:t#e8e 1.&>8(!nt Dens%ty
1$2U c%assis' 27J dept%
Up to 7 cores 8 1-2 2 1-69:5
> Up to ;6 t%reads
1; #<2+I&& "e"ory slots
> ;69< of "e"ory' =69< +I&&s>
<%?' 1e2%.6%2%ty
6 to 1; %ot plu* SAS 2-5J dis)
drive =RAI+ !'1>
(K( Redundant' %ot2swappa3le
PSUs and #ans- +C PSU option
for 1U syste"s only
E:9.n/.62e
0$; PCI2E epansion slots
=includin* 2 1! 9<E I$! slots>
6 193E Et%ernet as standard
6 US< ports
Opti"i5ed for 3est price $
perfor"ance / perfor"ance $ watt
Scale2Out of we3 / networ)
infrastructure
Etension to T1!!!$T2!!!
product line
A5aila'le Ao2
Sun &ire T1000 * T5120 %i((erences
Fe.t!#e S!n F%#e 31000 SP01C Ente#9#%se 35120
F(#8 F.&t(# 1U@ 1;AB /ee9 1U@ 2;B /ee9
CPU
Me8(#y
Net$(#> 4: 76E 4: 76E + 2: 1076E
Inte#n.2 St(#.?e
1e8(5.62e Me/%. N(ne 1: DCD-1DM
Se#%.2
PCI E:9#ess s2(ts
P($e# S!992y
F.ns N(n-<(t-S$.9 1e/!n/.nt<(t-S$.9
U2t#.SP01C 31
1-0 7<=@ 32 t'#e./s
U2t#.SP01C 32
1-21-4 7<= 64 t'#e./s
DD12 327B M.:
;: s2(ts
FB-DIMM 647B M0E
16: s2(ts
1: 3-5B S030@ n(n-'(t-s$.9
D1 2: 2-5B S0S
U9 t( ; : 2-5B S0S@ '(t-s$.9
1: 1S-232@ No USB 1: 1S-232@ 4: USB
1: (2($ 9#("%2e) 3:(2($ 9#("%2e)
1: 300+ 0C
N(n-1e/!n/.nt
2: 650+ 0C F DC (9t%(n
1e/!n/.nt<(t-S$.9
Sun &ire T2000 * T5220 %i((erences
Fe.t!#e S!n F%#e 32000 SP01C Ente#9#%se 35220
F(#8 F.&t(# 2U@ 24B /ee9 2U@ 2;B /ee9
CPU
Me8(#y
4: 76E 4: 76E + 2: 1076E
Inte#n.2 St(#.?e
1e8(5.62e Me/%. 1: DCD-1DM 1: DCD-1DM
Se#%.2
PCI E:9#ess s2(ts
PCI-E s2(ts N(ne
P($e# S!992y
U2t#.SP01C 31
1-0 - 1-47<= 32 t'#e./s
U2t#.SP01C 32
1-21-4 7<= 64 t'#e./s
DD12@ 647B M0E
16: S2(ts
FB-DIMM@ 647B M0E
16: S2(ts
Net$(#>(101001000)
4: 2-5B S0S@ '(t-s$.9 U9 t( 16 : 2-5B S0S@ '(t-s$.9
1: 1S-232@ 4: USB 1: 1S-232@ 4: USB
3:(2($ 9#("%2e) 6:(2($ 9#("%2e)
2 : (2($ 9#("%2e)
2: 450+ 0C
1e/!n/.nt<(t-S$.9
2: 750+ 0C
1e/!n/.nt<(t-S$.9
Sun Internal and Approved Partners Only 1;
&ront Panel
7IS, ) 7IS, 7IS, ( 7IS, /
7IS, )
7IS, 7IS, /
7IS, (
7IS, <
7IS, 3 7IS, + 7IS, F
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#-utton
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Status "E7
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Status "E7
Po2er -utton
Serial Aum'er la'el
Serial Aum'er
7isk 7ri5e Ma8
To8 !ault "E7
PSU !ault "E7
Tem8 !ault "E7
To8 !ault "E7
PSU !ault "E7
Tem8 !ault "E7
7isk 7ri5e Ma8
7@71B>M
7@71B>M
7ual US- (.) 8orts
7ual US- (.) 8orts
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7IS, 0
7IS, E
7IS,
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7IS, 3
Sun Internal and Approved Partners Only 1D
Rear Panel
PSU ) PSU
PSU
PSU )
PSU
Status
"E7Gs
SP
Serial
Port
9hassis
Status "E7Gs
an6 "ocator -utton
SP
Aet2ork
Port
Hua6 %iga'it
Ethernet Ports
7ual
US- (.)
Ports
P>SIX 7-1E
Serial Port
P9I1E Slot )#XAUI )
&0 Slot#&3 Electrical
P9I1E Slot #XAUI
P9I1E Slot (
P9I#XAUI ) P9I#XAUI P9I (
P9I#XAUI ) P9I#XAUI P9I (
P9I < P9I 3 P9I /
PSU
Status
"E7Gs
SP
Serial
Port
9hassis
Status "E7Gs
an6 "ocator -utton
SP
Aet2ork
Port
Hua6 %iga'it
Ethernet Ports
7ual
US- (.)
Ports
P>SIX 7-1E
Serial Port
Arc#itecture $lock %iagra! 0 T5120
7
1; #<2+I&&
=++R22;;D>
6 &e"ory Controllers' 2 C%annels' 2 +I&&S
+is) C%assis
1RU
6 ,SI
1!;7E
6 SAS lin)s
6
1
US<
to I+E
+4+
US<
2-!
2-!
2-!
Intel
+ual
93E
6 6
! 1 2 0 !
1!93E
Ser+es
<C&7D!6
L#P
1!93E
#i3re
Plu*in
1!93E
Cu P:C
<C&
7
6
7
6
US< 2-!
:u3
PCI2E
Switc%
P,L 7500
PCI2E
Switc%
P,L 7500
PCI2E
Switc%
P,L 751D
PCI2E
to
US<
Intel
+ual
93E
1!93E
1!93E
&PC775
I,O&
Service
Processor
#P9A
#ront Panel
US< .uad 93E
Connectors
PCI2E
1;
PCI2E
7
PCI2E
7
Serial
&*t
(etwor)
&*t
POSIL
Serial +<2E
Rear Panel
SSI
6
Sun Internal and Approved Partners Only 1E
Arc#itecture $lock %iagra! 0 T5220
7
1; #<2+I&&
=++R22;;D>
6 &e"ory Controllers' 2 C%annels' 2 +I&&S
+is) C%assis
1RU 2RU$7
6 ,SI
1!;7E
6
6 SAS lin)s
6
1
US<
to I+E
+4+
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2-!
2-!
2-!
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6 6
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1!93E
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7
7
6 6 6
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PCI2E
Switc%
P,L 7500
PCI2E
Switc%
P,L 7500
PCI2E
Switc%
P,L 751D
PCI2E
to
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Intel
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1!93E
1!93E
&PC775
I,O&
Service
Processor
#P9A
#ront Panel
US< .uad 93E
Connectors
PCI2E
1;
PCI2E
7
PCI2E
7
PCI2E
7
PCI2E
7
PCI2E
7
2RU Only
Serial
&*t
(etwor)
&*t
POSIL
Serial +<2E
Rear Panel
SSI
)nternal 2ie/ +T5120-
7isk
9hassis
SAS &3 ca'le
to
7isk 9hassis
3 !an Assem'lies are re?uire6
:chassis can take u8 to 0;
System 9on4iguration
9ar6 :S99;EEPB>M
P9I1E Slot (
&+:m;#&0:e;
9hassis Intrusion Bee6
S2itch
:magnet on un6ersi6e o4 li6;
X3 SAS 9onnector ) :ca'le attache6;
X3 SAS 9onnector :not use6 in BU;
Ser5ice Processor
!-17IMMs
UltraSPAB9
T(
Po2er
Su88lies
!-17IMMs
!-17IMMs
!-17IMMs
Po2er
-oar6
PSU
PSU)
P9I1E Slot
&0:m;#&3:e;
or
XAUI
P9I1E Slot )
&0:m;#&3:e;
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Po2er -US -ars
BE7 D I(@olts
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/ !an Assem'lies are re?uire6
:chassis can take u8 to +;
System 9on4iguration
EEPB>M
P9I1E Slot (
&0:m;#&0:e;
&+:m;#&0:e;
9hassis Intrusion Bee6
S2itch
:magnet on un6ersi6e o4 li6;
X3 SAS 9onnector ) :ca'le attache6;
X3 SAS 9onnector :ca'le attache6;
Ser5ice Processor
!-17IMMs
UltraSPAB9
T(
Po2er
Su88lies
!-17IMMs
!-17IMMs
!-17IMMs
Po2er
-oar6
PSUGs
@ertically
Stacke6
P9I1E Slot
&0:m;#&3:e;
&0:m;#&3:e;
or
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Me!ory P#ysical 3ayout
9hassis
!ront
9hassis
Bear
9hannel#7IMM #-ranch
9hannel#7IMM )#-ranch
9hannel)#7IMM #-ranch
9hannel)#7IMM )#-ranch
9hannel#7IMM #-ranch )
9hannel#7IMM )#-ranch )
9hannel)#7IMM #-ranch )
9hannel)#7IMM )#-ranch )
9hannel)#7IMM )#-ranch (
9hannel)#7IMM #-ranch (
9hannel#7IMM )#-ranch (
9hannel#7IMM #-ranch (
9hannel)#7IMM )#-ranch /
9hannel)#7IMM #-ranch /
9hannel#7IMM )#-ranch /
9hannel#7IMM #-ranch /
Memory Po8ulation Bules
. All -ranches must ha5e at least one
7IMM 8o8ulate6
1 min con4ig is 3 & %- 7IMMS
(. Po8ulate -ranches starting 2ith the
nearest slot to the 9PU 4irst
1 See J1K in the 6iagram
9)7)-), 9)7)-, 9)7)-(, 9)7)-/
/. All 7IMMS must 'e the same siCe
3. In -ranch all 7IMMS must 'e in6entical
:SUA Part Ao.;
1 U8gra6ing 4rom 3 to 0 7IMM
con4igs means mo5ing 7IMMS to
ensure sameness
<. ( 7IMM con4igurations are A>T
su88orte6.
+. >nly %-, (%- an6 3%- 7IMMS are
su88orte6
F. Memory is !-17IMM 77B(1++F, there
is no clocking 6o2n o4 memory in any
con4ig.

( (
( (
( (
( (
/ /
/ /
/ /
/ /
/ /
/ /
/ /
/ /
UltraSPARC
T2
Me!ory Con(iguration Rules
Populate at least 6 +I&&S at a ti"e
#irst
>
#ill +I&&! in C%annel ! in eac% <ranc%
Second
> #ill +I&&! in C%annel 1 in eac% <ranc%
T%ird
>
#ill re"ainin* +I&& slots-
All +I&&S "ust 3e t%e sa"e si5e=i-e all 19<' 29< or 69<' no
"iin*>
In a <ranc% all +I&&S "ust %ave t%e sa"e SU( Part (o-
12 +I&& confi*urations are (OT supported-
(o cloc)in* down of "e"ory in any confi*-
Me!ory Population E1a!ples

( (
( (
( (
( (
/ /
/ /
/ /
/ /
/ /
/ /
/ /
/ /
UltraSPARC
T2

( (
( (
( (
( (
/ /
/ /
/ /
/ /
/ /
/ /
/ /
/ /
UltraSPARC
T2

( (
( (
( (
( (
/ /
/ /
/ /
/ /
/ /
/ /
/ /
/ /
UltraSPARC
T2
3 7IMM
con4iguration
0 7IMM
con4iguration
+ 7IMM
con4iguration
'et/ork Ports and "ptions
XAUI )
A>TES
AET ) an6 AET share a common Intel >8hir chi8, as 6o AET ( an6 AET /.
XAUI A6a8ter car6s are re?uire6 to take a65antage o4 the 'uilt1in )%'E net2orking
There are t2o 5ariations, !i're an6 9o88er
!i're XAUI car6s take one o4 three current )%'E transcei5ers
Short Beach:SB;, "ong Beach:"B; an6 "ong Beach Multimo6e:"BM;
9o88er 5ersions o4 the XAUI car6 are e&8ecte6 Post1BB
XAUI 9ar6s consume the same 8hysical s8ace in the chassis as a P9I car6, so are mutually
e&clusi5e 2ith P9I car6s in the same location
Device NET 0 NET 1 NET 2 NET 3 XAUI 0 XAUI 1
Driver e1000g0 e1000g1 e1000g2 e1000g3 nxge0 nxge1
PCI Device PCI 0/0/1/0/2 PCI 0/0/1/0/3 NIU@80/0 NUI@80/1
XAUI
10.,E 4AU) "ption Cards
Interface to t%e outside world for t%e On3oard 2 1!93E interfaces
fro" t%e UltraSPARC T2
Cards eac% consu"e a PCI2E slot if installed
Attac% to dedicated LAUI soc)ets on special risers
1!93e LAUI Card
I
SESCDLA1M
> Re1uires #i3re Tranceivers
I 1!93E S%ort Reac%=SR>
I
SESCDLT1M
I 1!93E ,on* Reac% =,R>
I
SESCDLT2M
I 1!93E ,on* Reac% "ulti"ode =,R&>
I
part (o- T<+
Copper connector LAUI versions to follow post2RR
PC) Riser Cards
4arious Riser Cards are used
Risers s%ould not 3e "oved 3etween slots
All slots acco""odate low Profile PCI2Epress cards
T512! I 25 ?atts per card' D5 ?atts &a =0 Slots>
T522! I 25 ?atts per card' 1!2 ?atts &a =; Slots>
> Riser Card &ec%anical and Electrical widt%s for T512! and T522!
35120
S2(t 0 S2(t 1 S2(t 2
Dn2y S2(t :;E0UI(8) :4(e) :;E0UI(8) :4(e)
:16(8) :;(e)
35220
S2(t 1 S2(t 1 S2(t 2
3(9 S2(t :;(8) :4(e) :;(8) :4(e) :;(8) :;(e)
%isk Cage
+is) c%assis is a #RU
I 6 screws and disconnect ca3les
Contains +4+2RO&$+ual US< "odule as a
su32#RU$CRU
I Standard in all default confi*s
I re"ove dis) 0$D to access release latc%' pre2RR
(on2+4+ "odule availa3le as L2Option
I Still provides +ual US< ports
T512! will 3e availa3le initially wit% only a 6
dis) c%assis' 7 dis) in 1ualification
> Only uses one or two' of t%e 6 SAS lin)s
T522! will 3e availa3le initially wit% only an 7
dis) c%assis' 1; dis) in 1ualification
> Uses 3ot% of t%e 6 SAS lin) ca3les
Bemo5e 7isk an6 locate
latch 'eneath 7@7
Press u8 an6 8ull 7@7 out
%isk Cage 0 T5120
C%assis acco""odates up to 6 or 7 SAS or SATA 2-5J
drives
I (o "iin* in a c%assis
I (o c%assis c%an*es needed
+is) C%assis re1uires only a sin*le ca3le
Connects to #an Paddle 3oard wit% press fit connector
&ountin* ensures fan to dis) vi3ration isolation
GTG hea6
locator 'olts
"ocator Ta's
!an Pa66le
-oar6 8ress1
4it connector
&3 SAS ca'le
an6 connector
9hassis
Scre2s
9hassis
Scre2s
%isk Cage 0 T5220
Acco""odates up to 7 or 1; SAS or SATA
2-5J drives
Re1uires 3ot% SAS ca3les 3e connected
Two 6 SAS connector on c%assis
Even 1; dis)s provides lots of airflow
Ca*e and #an install ensures vi3ration
isolation
GTG hea6
locator 'olts
"ocator Ta's
Pa66le -oar6
8ress14it
connector
&3 SAS ca'les
an6 connectors
9hassis
Scre2s
9hassis
Scre2s
%isk %rives
+is) drives are all 2-5J for" factor
C%assis support 3ot% SAS and SATA =post2RR>
SAS +rives
I D09< 8 1!N RP&
I 16;9< 8 1!N RP&
I D09< 8 15N RP& =post2RR>
I 16;9< 8 15N RP& =post2RR>
SATA +rives
I 2!!9< 8 56!! RP& =soon after RR>
I 0!!9< 8 56!! RP& =:1CC!7>
I 5!!9< 8 D2!! RP& =end CC!7>
(ew "ountin* 3rac)et O&arlinJ
> Allows 3etter coolin* in denser c%assis
Bea6y to
Bemo5e
!ault
Status
7isk "E7Gs
Im8ro5e6
Air4lo2 a'o5e
an6 'elo2
6isks
%isk Controller "ptions
T52! %as e"3edded ,SI1!;7E on t%e "ot%er3oard
I P<O+ up to 7 dis)s
I Controls internal dis)s only
I RAI+ ! =stripin*> and RAI+ 1="irrorin*>
I :ot2plu* supported
I :ot2swap in non2RAI+ confi*s is done wit% Qcf*ad"Q
Optional Etended RAI+ functionality cards =availa3le .6CC!D>
> QCou*arQ 2 S9LPCIESAS2R2I(T2M
I 7 port SAS RAI+ !'1'1E'5'5EE';'1!'5!';! =dependin* on (o- dis)s availa3le>
I Adaptec Card and #ir"ware wit% Intel SunRise,a)e c%ipset
I <attery <ac)ed ?rite Cac%e =<<?C> of 25;&<
I <<?C 3attery at least D2 %ours ="uc% lon*er w%en new$fully c%ar*ed>
I Only for internal dis)s' replaces ca3les to route to standard dis) c%assis
> QPro"et%eusQ I S9LPCIESAS2R2ELT2M
I Eternal port version of QCou*arQ' for eternal dis) arrays only =no internal ports>
&ans and Cooling
T512!
> Re1uires 6 #an "odules
> Two coolin* *roups
I 9roup 1 I (2 coolin*
I
#A(<+!$#&1
I
#A(<+1$#&1
I 9roup 2 I #<2+I&& coolin*
I
#A(<+1$#&!
I
#A(<+1$#&2
I <lan) &odule in #A(<+1$#&0
T522!
> Re1uires 0 #an &odules
> Sin*le *roup for (2 and #<2+I&&
I #A(<+!$#&!
I #A(<+!$#&1
I #A(<+!$#&2
:i*%er dis) densities "ay re1uire "ore fans
PSUGs PSUGs
!
-
7
!
-
7
!
M
/
!
M
/
!
-
7
!
-
7
!
M
(
!
M
(
!
-
7
!
-
7
!
M
!
M
!
-
7
!
-
7
!
M
)
!
M
)
!
-
7
)
!
-
7
)
!
M
)
!
M
)
!
-
7
)
!
-
7
)
!
M
!
M
!
-
7
)
!
-
7
)
!
M
(
!
M
(
!
-
7
)
!
-
7
)
!
M
/
!
M
/
Mother'oar6 Mother'oar6
7
i
s
k

9
h
a
s
s
i
s
7
i
s
k

9
h
a
s
s
i
s
PSUGs PSUGs
Mother'oar6 Mother'oar6
7
i
s
k

9
h
a
s
s
i
s
7
i
s
k

9
h
a
s
s
i
s
!
-
7
)
!
-
7
)
!
M
!
M
!
-
7
)
!
-
7
)
!
M
)
!
M
)
!
-
7
)
!
-
7
)
!
M
(
!
M
(
!
-
7
!
-
7
!
M
!
M
!
-
7
!
-
7
!
M
)
!
M
)
!
-
7
!
-
7
!
M
(
!
M
(
!ront -ack
&ans !odules and ,oards
#ans are speed controlled 3y t%e Service
Processor
Eac% fan %as an A"3er #AU,T ,E+
I if lit t%e fan "odule is faulty
1RU "odules
I 2 #ans at 15N RP& &a-
2RU "odules
I 2 #ans at 12N RP& &a
&onitored t%rou*% I,O&$IP&I$?e3
!an !ault
Am'er "E7
"it i4 4an
4aulty
@i'ration
A'sor'ing
Silicon
7am8ers
Po/er Supplies
PSUQs are %i*% efficiency
Output 124 =and 0-0v stand3y>
&ost +C2+C conversion done in &<+
S%ared wit% +oradi$o' Tucani$a
Inte*rated #an
T512!
> Side23y2Side
> AC ;5!?atts
> +C ;;! ?atts option co"in* post2RR
> +C or AC' no s%arin*
T522!
> 4ertically Stac)ed
> D5!?atts ="ay re1uire t%e 1!5!?att Psu for t%e 1; dis) c%assis' pendin* 1uals>
> (o +C option
> <E?ARE--- Sa"e for" factor as Sun#ire L62!! PSUQs --- +O (OT &IL
Bea6y to
Bemo5e
!ault
A9
Present
PSU "E7Gs
Rack Mounting "ptions
Two Rac) "ountin* options are availa3le--
Standard Rac) &ount =6 post>SESCERN1M
>
Sa"e as 9alay servers' T2!!!' etc--
>
Standard confi*s contain t%is )it
I ATO @ SESCERN1M' L2ATO @ SESCERN1M
Tool2less Rac) Nit =6 post>
>
Optional )it' purc%ased seperately
>
Snaps into "ost 0
rd
party Rac)s
>
Re1uires no tools to fit or re"ove
I ATO @ SESCERN2M' L2ATO @ SESLERN2M
Solaris (or Sun SPARC Enterprise T5120
T52! servers will re1uire Solaris1! 7$!D =update 6>
T%is incorporates several UltraSPARC T1$T2
opti"isations for C&T servers in *eneral
Also includes so"e specific T52! opti"isations
>
UltraSPARC T2 Crypto opti"isations
>
n*e driver for 1!93E devices
>
UltraSPARC T2 perfor"ance counters
>
Processor *roupin*' pa*e colorin* and default si5in* and
3copy$"e"cpy
Solaris &MA (or T5120
(ow aware of CPU Core oflinin*
PCIe #a3ric dia*nostics i"proved
Crypto Unit offlinin*
(etwor) interface Units =1!93E>
POST "e"ory CE tolerance i"proved
#RU identity info i"proved in fault reports =part$ser R>
+ia*nostic En*ines =+E>
I Eistin* +E %ave 3een etended for T52!
I (ew Evers%olt +E used for :ost<rid*e' PCIe and (UI dia*nostics
,i"itations---
I
CanQt isolate Uncorrecta3le Errors to a sin*le +I&&
I
PCIe riser cards not in topolo*y
I
LAUI card and L#P not in t%e topolo*y
I
Sout%<rid*e c%ip is not dia*nosed at t%is ti"e =+4+' US<'--->
Agenda
Introduction
> Solaris for T52!
I,O& 2-!
,+O&s for T52!
. / A ---
)3"M &eatures at a .lance
:ardware Control' Inventory' &onitorin*
:ost Confi*uration and Ad"inistration
SP Confi*uration and Ad"inistration
,o**in*' Auditin* and Alertin*
Aut%entication @
I ,+AP' RA+IUS' Active +irectory' ,ocal Users
Services @
I SS:' :TTP=S>' (TP' Syslo*' S&TP
Out2of2<and
I 4ia Serial port' or dedicated Et%ernet port
In2<and
I 4ia :ost OS' fir"ware upload' Eplorer' Syslo*
)3"M 5 )ndustry Standard Managea,ility
I,O& ena3les Sun syste"s to 3e easily inte*rated into
t%ird party "ana*e"ent infrastructures
Ney functionality
> IP&I 2-!
> S(&P 41' 42c' 40
> SS: 2-!
> ,+AP' RA+IUS / &S Active +irectory aut%entication
> <rowser UI' S&AS: +&T# C,P K A,O& style C,I
(OTE @ (o RN4&S functionality li)e 9alay I,O&
>
(o Pava plu*in re1uired
<rowsers tested include
I &o5illa 1-D on Solaris 1!' IE ;-! on ?2N Server'
#irefo 1-! and 1-5 on ?2N server
)3"M 5 )ndustry Standard Managea,ility
+efault user is QrootQ wit% password QchangemeQ
>
Use for I,O& ?E< 9UI access and SS: access and
IP&I
T%e A,O& QadminQ user is not defined 3y default' create
t%is user wit% an A,O& C,I
,ost QrootQ password and I,O& confi* is reset usin*
&ot%er3oard Pu"per P;7!1
(ote--- QsunserviceQ user s%ares t%e password of t%e
QrootQ user DNLG FD1 SE1CICE 0CCESSS
Passwords "ust 3e 7 to 1; c%ars =used to 3e "a 7>
&a of 1! users allowed =used to 3e 1;>
)3"M Co!!on Tasks
Settin* up an A,O& Qad"inQ user fro" t%e I,O& C,I
>
SUNSP00144F4641BD login: root
Password: changeme
Waiting or daemons to initiali!e"""
Daemons read#
Sun$%&' (ntegrated )ights *ut &anager
+ersion ,"0"4"0
-o.#right ,00/ Sun &icros#stems0 (nc" 1ll rights reserved"
Use is su23ect to license terms"
Warning: .assword is set to actor# deault"
45create 6SP6users6admin role71dministrator cli8mode7alom
-reating user"""
9nter new .assword: ::::::::
9nter new .assword again: ::::::::
-reated 6SP6users6admin,
45 e;it
SUNSP00144F4641BD login: admin
Password: ::::::::
Daemons read#
+ersion ,"0"4"0
sc5
)3"M Co!!on Tasks
Settin* up I,O& IP confi*uration fro" t%e I,O& C,I
>
SUNSP00144F4641BD login: root
Password: changeme
Daemons read#
+ersion ,"0"4"0
Warning: .assword is set to actor# deault"
45 set 6SP6networ< state7ena2led
Set =state= to =ena2led=
45 set 6SP6networ< .endingi.address710">"?1"16?
Set =.endingi.address= to =10">"?1"16?=
45 set 6SP6networ< .endingi.discover#7static
Set =.endingi.discover#= to =static=
45 set 6SP6networ< .endingi.netmas<7,@@",@@",@,"0
Set =.endingi.netmas<= to =,@@",@@",@,"0=
45 set 6SP6networ< .endingi.gatewa#710">"?1",4>
Set =.endingi.gatewa#= to =10">"?1",4>=
45 set 6SP6networ< commit.ending7true
Set =commit.ending= to =true=
45
45 set6SP6.endingi.discover#7dhc.
Set =.endingi.discover#= to =dhc.=
45 set 6SP6networ< commit.ending7true
Set =commit.ending= to =true=
45
Static IP
con4iguration
7ynamic IP
:7$9P;
con4iguration
)3"M )PM) (unctionality
IP&I is a widely used "ana*e"ent protocol for 7; servers
--- <ut its new for SPARC 3oes---
+ownload t%e re1uired tools fro"
> T%e Solaris Supple"ental C+ =an older 3inary pac)a*e>
> ,atest is availa3le at %ttp@$$ip"itool-sourcefor*e-net
I <inary pac)a*es =usually older versions> are availa3le for Solaris 7; and
SPARC' as well as ,inu' ?indows' &ac---etc
> T%ere is a <lueprint availa3le fro" Sun also ="ainly;6 centric' 3ut applies to
SPARC now too>
I
%ttp@$$www-sun-co"$3lueprints$!1!D$72!21!11-pdf
42ash4ventus,A 6o.t6i.mitool62in6i.mitool 4U root 4P changeme 4B 10"10"10"10 sdr
6&B6+8C1+08+DD D 1"01 +olts D o<
6&B6+8C?+?8S%BE D ?"?6 +olts D o<
6&B6+8C?+?8&1(N D ?"?6 +olts D o<
6&B6+8C@+08+-- D 4"F/ +olts D o<
6&B6+8C1,+08&1(N D 1,"16 +olts D o<
""
""
42ash4ventus,A 6o.t6i.mitool62in6i.mitool 4U root 4P changeme 4B 10"10"10"10sunoem
s2led set 6SES6)*-1%9 on
6SES6)*-1%9 D *N
42ash4ventus,A
%et the
Sensor 7ata
Be8ository
Set the System
"ocator "E7
4lashing
)3"M Co!!on Tasks
,o**in* into t%e I,O& ?e3 9UI
Point ?e3 <rowser at t%e IP address
of t%e I,O&
> ?ill auto"atically redirect to a
secure :TTPS port
> <est to disa3le any ?e3
Proies for 3est perfor"ance
> &a)e sure port 7!' 660 are
open on any firewall
,o* in as any defined user' default
Ad"inistration user is QrootQ
)3"M*A3"M Co!!on Tasks
A Tour of t%e I,O& ?e3 9UI
9UI provides ways to set up IP address
confi*urations for I,O&
Confi*ure additional I,O&$A,O& users
Access Sensor Readin*s
Control Syste" confi*urations
Carry out fir"ware updates-
etc----
A3"M 260 vs6 167 C3) %i((erences
+efault C,I appearance is I,O&
I User is QrootQ
I &ust create an QadminQ Ad"inistrator user wit% t%e A,O& C,I
#las%update in new A,O& epects a T#TP server not an #TP server
A,O& IP address c%an*es now active only after runnin* ---
I Qsetsc netsc8commit trueQ
I Previously c%an*es were active only after SC reset
I +:CP is ena3led 3y default
4iew fir"ware versions wit%
I Qshowhost versionQ
4iew #P9A version wit%
I Q.ga versionQ
Only Ad"in and Operator roles
are defined
sc5 showhost version
Sun S#stem Firmware /"0"082uild81? ,00/60>610 ,?:44
Bost lash versions:
B#.ervisor 1"@"0"2uild81?::PH*%*%EP9:: ,00/60>610 ,,:@4
*BP 4",/"0"2uild804:::PH*%*%EP9 BU()D::: ,00/60>610 1?:,@
Sun FireI%&J Buron P*S% 4",/"0"2uild804:::PH*%*%EP9 BU()D:::
,00/60>610 1?:@1
sc5 .ga version
FPK1 +ersion: 1"@"0"0
Platorm (D : 1
&a3or revision : @
&inor revision : 0
)a2 De2ug +ersion: 0
sc5

A3"M ,ack/ard Co!pati,ilty C3)
Uses A,O&2C&T 1-2 for a 3ase feature set
Includes A,O&2C&T 1-6 features---
>
3rea) 2d
>
:ost ?atc%do* Ti"er
>
<oot"ode ,+O&s awareness
>
#orward SP events to :ot$Solaris syslo* via in3and
c%annel
Agenda
Introduction
> Solaris for T52!
I,O& 2-!
,+O&s for T52!
. / A ---
3ogical %o!ains 16061 &eatures
UltraSPARC T2 Platfor" Support
> 02 do"ains at RR' ;6 do"ains followin*
I$O do"ain can re3oot w%ile t%e ot%er do"ains )eep
runnin*
> +ependant do"ains would wait for IO transactions to co"plete
,+o"s S(&P &I<
> &odeled after industry standard +&T# CI& =Co""on Infor"ation
&odel>
> Runnin* on control do"ain to ena3le re"ote S(&P "onitorin*
+o"ain "ini"i5ation support
> &ini"al$reduced Solaris installation
> <ase "ini"al pac)a*es plus optional ones for *uest' control' I$O or
service do"ains
Belease6, aligne6 2ith UltraSPAB9 T(#T<&()
3ogical %o!ains 16061 Re8uire!ents
Solaris 1! !7$!D =update 6>
Syste"s fir"ware version
I T52!$9lendale #ir"ware D-!- B SP #? 2-!-6-!K
I T2!!!$T1!!!$T;0!!$Pelton #ir"ware ;-5-
SU(?ld"-v ,+O&s &ana*er Pac)a*e
I 4ersion 1-!-1
T52! Syste" #P9A
I 4ersion 1-5-!K =(ot a concern for Post2RR syste"s>
Agenda
Introduction
> Solaris for T52!
I,O& 2-!
,+O&s for T52!
. / A ---
CRU*&RU 3ist 0 T5120
,ots s%ared wit% ot%er Pa)e and Elwood syste"s
I te8 Des&#%9t%(n F1UC1U
D%s> B.&>92.ne 4 /#%5e D%s> B.&>92.ne t( s!99(#t 4 D#%5es (n2y F1U
F.n M(/!2e 1U D!.2 F.n 8(/!2e@ 4 9(9!2.te/ %n syste8 C1U
F.n B(.#/ 1U F.n &(nne&t(# 6(.#/ t( .&&(88(/.te F.n M(/!2es@ 2 9e# syste8 F1U
DCD 0sse862y DCD 0sse862y %n&2!/%n? "#(nt USB 6(.#/ F1U
P.//2e 6(.#/ 1U C(ne&t%(n 6et$een PDB@ ".n 6(.#/s .n/ D%s> B.&>92.ne F1U
PDB 1U F1U
PSU 1U P($e# s!992y (650 +.tts) C1U
E; FE0UI @ 1U PCIe 1%se# PCI 1%se# .sse862y "(# 2e"t .n/ &ent#e 8(t'e#6(.#/ s2(ts C1U
:16 1U PCI e 1%se# PCI 1%se# "(# #%?'t 8(t'e#6(.#/ s2(t C1U
1.&> 8(!nt >%t (#e4!%#es t((2s) 1.&> 8(!nt >%t C1U
1.&> M(!nt H%t (t((2ess) 1.&> 8(!nt >%t@ n( t((2s #e4!%#e/ "(# %nst.22.t%(n C1U
CM0 C.62e 8.n.?e8ent .#8 C1U
B!s B.#s P($e# B!s B.#s 6et$een PDB .n/ M(t'e#6(.#/ F1U
PDB t( MB 1%66(n C.62e 1%66(n &.62e "(# &(nt#(2 &(nne&t%(ns 6et$een PDB .6/ M(t'e#6(.#/ F1U
L%?'t 9%9e >%t L%?'t 9%9e .sse862%es "(# 2e"t .n/ #%?'t (" /%s> &.?e F1U
M(t'e#6(.#/ .sse862y M(t'e#6(.#/ .sse862y@ 9.#t n( 5.#%es /e9en/%n? (n C(#e &(!nt F1U
DI MMs FBDIMMs (t'#ee /%""e#ent 9.#t n!86e#s "(# 17B@ 27B@ 47B) C1U
E0UI 6(.#/ (9t%&.2&(99e# E0UI 0/.9te# &.#/ (t$( /%""e#ent 9.#ts "(# &(99e#(9t%&.2) C1U
EFP 8(/!2e EFP 7BI C 8(/!2e "(# !se %n E0UI &.#/s (t'#ee /%""e#ent 9.#ts S1@ <1@ <1MM) C1U
B.tte#y B.tte#y 6.&>!9 "(# NC10M (" Se#5%&e P#(&ess(# C1U
<DD 737B1467B S0S <.#/ D%s> /#%5e@ /%""e#ent 9.#t n!86e#s "(# &.9.&%t%es C1U
Syste8 C(n"%?!#.t%(ns P1DM Syste8 C(n"%?!#.t%(n P1DM F1U
P($e# /%st#%6!t%(n 6(.#/@ &(nt.%ns 8.ste# &'.ss%s se#%.2 n!86e#
CRU*&RU 3ist 0 T5220
,ots s%ared wit% ot%er Pa)e and Elwood syste"s
I te8 Des&#%9t%(n F1UC1U
D%s> B.&>92.ne ; /#%5e D%s> B.&>92.ne t( s!99(#t ; D#%5es (n2y F1U
F.n M(/!2e 2U D!.2 F.n 8(/!2e@ 3 9(9!2.te/ %n syste8 C1U
F.n B(.#/ 2U F.n &(nne&t(# 6(.#/ t( .&&(88(/.te F.n M(/!2es@ 2 9e# syste8 F1U
DCD 0sse862y DCD 0sse862y %n&2!/%n? "#(nt USB 6(.#/ F1U
P.//2e 6(.#/ 2U C(nne&t%(n 6et$een PDB@ ".n 6(.#/s .n/ D%s> B.&>92.ne F1U
PDB 2U F1U
PSU 2U P($e# s!992y (750 +.tts) C1U
E;@E;@ E0UI @ 2U PCI e 1%se# PCI 1%se# .sse862y "(# 2e"t .n/ &ent#e 8(t'e#6(.#/ s2(ts C1U
E;@ :16 2U PCI e 1%se# PCI 1%se# "(# #%?'t 8(t'e#6(.#/ s2(t C1U
1.&> 8(!nt >%t (#e4!%#es t((2s) 1.&> 8(!nt >%t C1U
1.&> M(!nt H%t (t((2ess) 1.&> 8(!nt >%t@ n( t((2s #e4!%#e/ "(# %nst.22.t%(n C1U
CM0 C.62e 8.n.?e8ent .#8 C1U
B!s B.#s P($e# B!s B.#s 6et$een PDB .n/ M(t'e#6(.#/ F1U
PDB t( MB 1%66(n C.62e 1%66(n &.62e "(# &(nt#(2 &(nne&t%(ns 6et$een PDB .6/ M(t'e#6(.#/ F1U
L%?'t 9%9e >%t L%?'t 9%9e .sse862%es "(# 2e"t .n/ #%?'t (" /%s> &.?e F1U
M(t'e#6(.#/ .sse862y M(t'e#6(.#/ .sse862y@ 9.#t n( 5.#%es /e9en/%n? (n C(#e &(!nt F1U
DI MMs FBDIMMs (t'#ee /%""e#ent 9.#t n!86e#s "(# 17B@ 27B@ 47B) C1U
E0UI 6(.#/ (9t%&.2&(99e# E0UI 0/.9te# &.#/ (t$( /%""e#ent 9.#ts "(# &(99e#(9t%&.2) C1U
EFP 8(/!2e EFP 7BI C 8(/!2e "(# !se %n E0UI &.#/s (t'#ee /%""e#ent 9.#ts S1@ <1@ <1MM) C1U
B.tte#y B.tte#y 6.&>!9 "(# NC10M (" Se#5%&e P#(&ess(# C1U
<DD 737B1467B S0S <.#/ D%s> /#%5e@ /%""e#ent 9.#t n!86e#s "(# &.9.&%t%es C1U
Syste8 C(n"%?!#.t%(ns P1DM Syste8 C(n"%?!#.t%(n P1DM F1U
P($e# /%st#%6!t%(n 6(.#/@ &(nt.%ns 8.ste# &'.ss%s se#%.2 n!86e#
"ption Parts 3ist
P.#t N!86e# D9t%(n Des&#%9t%(n 05%.2.62e
SECG*PS11I 0C PSU 11U (650 +.tts) 11
SEDG*PS31I 0C PSU 21U (750 +.tts)
11
SECG*PS21I DC PSU 11U (660+.tts) 9(st-11
SESG201I 27B Me8(#y (2:17B)
11
SESG2B1I 47B 8e8(#y (2:27B) 11
SESG2C1I ;7B Me8(#y (2:47B) 11
SESG3011I 737B@ 10H198 2-5B S0S D#%5e 11
SESG3C11I 1467B@ 10H198 2-5B S0S D#%5e 11
- S030 D#%5es (200@ 300@5007B) 9(st-11
SESG*DC1I DCD@ ;E 1+@ S2(t L(./ 11
SESG*1H1I S2%/e 1.%2 H%t@ #e4!%#es s&#e$/#%5e# (11U .n/ 21U) 11
SESG*1H2I S2%/e 1.%2 H%t@ 3((2-2ess (11U .n/ 21U) 11
"ption Parts 3ist +cont66-
P.#t N!86e# D9t%(n Des&#%9t%(n 05%.2.62e
S7-PCIE1FC-JF4 J2(?%&@ 476@ PCI-E S%n?2e P(#t (!9 t( 36) 11
S7-PCIE2FC-JF4 J2(?%&@ 476@ PCI-E D!.2 P(#t (!9 t( 36)
11
S7-PCIE1FC-EM4 E8!2e:@ 476@ PCI-E S%n?2e P(#t (!9 t( 36) 11
S7-PCIE2FC-EM4 E8!2e:@ 476@ PCI-E D!.2 P(#t (!9 t( 36)
11
S7-PCIE2SCSI-U320I U320 SCSI@ PCI-E D!.2 P(#t (!9 t( 36) 11
S7-PCIE;S0S-E-I S0S@ ; P(#t@ PCI-E (!9 t( 1) 11
S7EPCIES0S-1-IN3-I S0S@ ; P(#t@ 10ID@ PCI-E Inte#n.2 D#%5e C(nt#(22e# (!9 t( 1) 11+3
S7CPCIES0S-1-EE3-I S0S@ ; P(#t@ 10ID@ PCI-E@ E:te#n.2 D#%5e C(nt#(22e# (!9 t( 1) 11+3
72;00-2 N(#t'st.# D!.2 9(#t 7%?E MMF L($ 9#("%2e PCI-E (!9 t( 36) 11
72;10-2 N(#t'st.# D!.2 9(#t 7%?E U3P L($ 9#("%2e PCI-E (!9 t( 36) 11
12360-I In"%n%6.n/ <B0@ D!.2 4: 9(#ts@ PCI-E (!9 t( 36) 11
44470-E 0t2.s J!./ P(#t@ 7%?E C(99e#@ PCI-E (!9 t( 36) 11
E42400 EC1-300@ PCI-E :16:; 7#.9'%&s &.#/s (!9 t( 1) 3BD
Agenda
Introduction
> Solaris for T52!
I,O& 2-!
,+O&s for T52!
. / A ---
Tuning "ut o( t#e $o1
Usin* Solaris 1! !7$!D---
>
+efault pa*es si5es for
I
Initdata Se*"ents is ;6)< pa*es
I
Private Anon' :eap' Process Stac)' Tet' S%ared Anon se*"ents are
6&< pa*es
I
IS& and +IS& use 25;&< pa*es
I
(ew varia3les introduced to control t%ese si5es if c%an*es are needed
I "aTu%eapTlpsi5e'"aTustac)Tlpsi5e' "aTpriv"apTlpsi5e'
"aTs%"Tlpsi5e' "aTuidataTlpsi5e' "aTutetTlpsi5e'
"aTs%"Tlpsi5e
>
,2 Cac%e %as%in* i"ple"ented
I
%elps rando"ise accesses to ,2 cac%es and ease t%ras%in*
>
Stac) 3iasin* i"ple"ented
I
+2Cac%e is only 6 ?ay associative--- 7 t%reads
I
Runnin* "ultiple copies of a 3inary can lead process stac)s ali*nin* in
t%e cac%e and to %ot lines in t%e cac%e
I
Stac) <ias slews t%e stac) varia3le for processes-
>
Sun Internal and Approved Partners Only ;!
Tuning "ut o( t#e $o1 +continued66-
>
Processor 9roups introduced
I
:elps associate CPUs wit% so"e s%ared resources =int$#P pipelines'
Crypto units etc>
I
Ena3les i"proved "ulti2level C&T load 3alancin* and affinity policies
>
Q3copyQ$Quio"oveQ Opti"i5ations
I
Ney )ernel operations
I
new i"ple"entation a3out 2 faster t%an previous
So"e opti"isations did not "a)e it into S1! 7$!D
>
T%ese will 3e post RR patc%es as t%ey 3eco"e availa3le
>
&ost fies are already co""itted in update 5
>
C%ec) patc% levels for custo"ers wit% perfor"ance issues
>
Also c%ec) #ir"ware versions as t%is can i"prove
perfor"ance too---
Sun Internal and Approved Partners Only ;1
Tuning Reco!!endations
,ess involved t%an wit% T2!!!
S1! 7$!D is "ore Qauto"aticQ
I OO< opti"ised pa*e si5e selection' t%read sc%edulin*' 3loc) copy' IP
instances for 5ones' pa*e colorin* etc---
If tunin* is necessary re"e"3er---
> I"proved pipeline results in Sin*le t%readed perfor"ance around 2!G 3etter
> #loatin* Point is no lon*er an issue
> Start wit% T2!!! tunin* options
> Use updated trapstat' cpustat'
,+O&s "ay 3e an easier way to scale poorly t%readed applications
Solaris Crypto fra"ewor) is still 3ein* tuned
> 9reat for 3i* pac)ets' wor)in* on i"provin* s"all pac)ets
A <lueprint is 3ein* prepared =+enis S%ea%an>
Tuning Reco!!endations +cont66-
Refer to UltraSPARC T1 applications tunin* 3est practices---
> %ttp@$$www-sun-co"$servers$coolt%reads$tn3$applications-Usp
CoolTools are 3ein* updated for UltraSPARC T2
> %ttp@$$www-sun-co"$servers$coolt%reads$overview$cooltools-Usp
Sun Studio 12 is UltraSPARC T1 and T2 aware
> Reco"pilin* wit%out code c%an*es s%ould 3enefit T1$T2 apps
Processes are 3ein* wor)ed on for ,+O&S "i*rations 1-! to 1-!-1
> ,+O&s confi*s can 3enefit fro" a transition to T52! platfor"
> &a)e sure appropriate ,+O&s tunin* and si5in* is carried out
?ider Crypto capa3ility' so ensure code is usin* PNCSR11 fra"ewor)
> Ensure t%at t%e ncp =SS,' RSA' +SA etc> and n2cp =3ul) cip%ers>'
n2rn*=rando" nu"3er *enerator> drivers are used appropriately

Agenda
Introduction
> Solaris for T52!
I,O& 2-!
,+O&s for T52!
. / A ---
Tools and )n(or!ation
Cool Tools
I %ttp@$$www-sun-co"$servers$coolt%reads$overview$cooltools-Usp
Arc%itecture ?%itePaper
I %ttp@$$www-sun-co"$
SU(?I( To)ens
>
Sun Intro @ 51661;
>
Arc%itecture ?%itepaper @ 512D5!
>
T%is Tec%nical Presentation@ 512D6E
Re(erence )n(or!ation
T512! and T522! =:uron> En*ineerin* TOI
I %ttp@$$ittdev-east-sun-co"$Tec%Tal)2$En*ineerin*TOIs$:uronTApr!D$
I,O&$A,O& User 9uides
I %ttp@$$www-sun-co"$products2n2solutions$%ardware$docs$pdf$71E211;!210-pdf
I %ttp@$$www-sun-co"$products2n2solutions$%ardware$docs$pdf$71E2DE7121!-pdf
Solaris #&A
I %ttp@$$f"a-en*
I %ttp@$$li*%tside-sf3ay$n22f"a$docs-p%p
;;
Pete# 0- +%2s(n
Senior Tec%nical &ar)etin* En*ineer
Sun &icrosyste"s
;;
Sun Internal and Approved Partners Only ;D
9uron PC) Topology
T5120 PC) %evice Tree
UltraSPARC T2 PCI 3us
To #irst ,evel PCI2E Switc% C%ip
To Second level PCI2E Switc% C%ip
TO Sout%<rid*e US< +evices
Standard US< +evice "ana*er
En%anced US< +evice "an*er
US< +ual Port :U<
Rear Port !
Rear Port 1
US< to I+E Converter
+4+ RO& +rive
#ront US< Port !
#ront US< Port 1
To +ual 93E Controller !
(IC !
(IC 1
To +ual 93E Controller 1
(IC 2
(IC 0
To SAS Controller
SAS Controller
SAS +is) +evice
To Second ,evel PCI2E Switc% C%ip
PCI2E Slot 1$2RU
PCI2E Slot !$2RU
PCI2E Slot 2$2RU
PCI2E Slot 1$1RU
PCI2E Slot !$1RU
PCI2E Slot 2
(etwor) Interface Unit
1!93T(IC !
1!93T(IC 1
O$pci8!V ! VpV
O$pci8!$pci8!V ! Vp3TplV
O$pci8!$pci8!$pci81V 1 Vp3TplV
O$pci8!$pci8!$pci81$pci8!V 0 Vp3TplV
O$pci8!$pci8!$pci81$pci8!$pci81V 6 Vp3TplV
O$pci8!$pci8!$pci81$pci8!$pci81$pci8!V ! VpTpciV
O$pci8!$pci8!$pci81$pci8!$pci81$pci8!$us38!V ! Vo%ciV
O$pci8!$pci8!$pci81$pci8!$pci81$pci8!$us38!'1V 1 Vo%ciV
O$pci8!$pci8!$pci81$pci8!$pci81$pci8!$us38!'2V ! Ve%ciV
O$pci8!$pci8!$pci81$pci8!$pci81$pci8!$us38!'2$%u386V ! V%u3dV
O$pci8!$pci8!$pci81$pci8!$pci81$pci8!$us38!'2$%u386$)ey3oard81V 2 V%idV
O$pci8!$pci8!$pci81$pci8!$pci81$pci8!$us38!'2$%u386$)ey3oard82V ! V%idV
O$pci8!$pci8!$pci81$pci8!$pci81$pci8!$us38!'2$stora*e81V ! Vscsa2us3V
O$pci8!$pci8!$pci81$pci8!$pci81$pci8!$us38!'2$stora*e81$dis)8!'!V ! VsdV
O$pci8!$pci8!$pci81$pci8!$pci81$pci8!$us38!'2$stora*e81$dis)8!'1V 0 VsdV
O$pci8!$pci8!$pci81$pci8!$pci81$pci8!$us38!'2$stora*e82V 1 Vscsa2us3V
O$pci8!$pci8!$pci81$pci8!$pci81$pci8!$us38!'2$stora*e82$dis)8!'!V 2 VsdV
OQpci8!$pci8!$pci81$pci8!$pci81$pci8!$us38!'2$stora*e80V 2 Vscsa2us3V
OJpci8!$pci8!$pci81$pci8!$pci81$pci8!$us38!'2$stora*e80$dis)8!'!V 6 VsdV
O$pci8!$pci8!$pci81$pci8!$pci82V 5 Vp3TplV
O$pci8!$pci8!$pci81$pci8!$pci82$networ)8!V ! Ve1!!!*V
V$pci8!$pci8!$pci81$pci8!$pci82$networ)8!'1V 1 Ve1!!!*V
V$pci8!$pci8!$pci81$pci8!$pci80V ; Vp3TplV
V$pci8!$pci8!$pci81$pci8!$pci80$networ)8!V 2 Ve1!!!*V
V$pci8!$pci8!$pci81$pci8!$pci80$networ)8!'1V 0 Ve1!!!*V
V$pci8!$pci8!$pci82V 2 Vp3TplV
V$pci8!$pci8!$pci82$scsi8!V ! V"ptV
V$pci8!$pci8!$pci82$scsi8!$sd8!'!V 1 VsdV
V$pci8!$pci8!$pci87V D Vp3TplV
V$pci8!$pci8!$pci87$pci8!V E Vp3TplV
V$pci8!$pci8!$pci87$pci8!$pci81V 1! Vp3TplV
V$pci8!$pci8!$pci87$pci8!$pci82V 11 Vp3TplV
V$pci8!$pci8!$pci87$pci8!$pci87V 12 Vp3TplV
V$pci8!$pci8!$pci87$pci8!$pci8EV 10 Vp3TplV
V$pci8!$pci8!$pci87$pci8!$pci8aV 16 Vp3TplV
V$pci8!$pci8!$pci8EV 7 Vp3TplV
V$niu87!V ! Vniu"V
V$niu87!$networ)8!V ! Vn*eV
V$niu87!$networ)81V 1 Vn*eV

T5120 and T5220 TTT

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T5120 and T5220 TTT

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Sun SPARC Enterprise

Sun Internal and Approved Partners Only ;0

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