Integrated Electronics

Lecture-2-5
Digital IC design Technologies
1
Digital Logic Circuit Families
CMOS Bipolar BICMOS e!s
Complementar"
MOS
#seedo
$MOS
#ass Transistor
Logic
#MOS
$MOS
TTL
%CL
&TL DTL
I2L
2
Operational Characteristic o'
Digital ICs

Logic Le(el

$oise Immunit"

$oise Margin

#ropagation Dela"

Fan In)Fan out

#o*er Dissipation

Dela" #o*er #roduct

Silicon !rea
+
Logic Le(els 'or TTL
,
Logic Le(els 'or CMOS
5
$oise Immunit"

The a-ilit" o' an apparatus or s"stem to

per'orm its 'unctions *hen inter'erence
.noise/ is present0

Thehigherthele(elo'noiseat*hichthe
e2uipmentmaintainsitsoperatinga-ilit"3the
higheritsnoiseimmunit"0

In order to not e''ected -" noise3 a logic circuit

must ha(e the certain amount o' noise
immunit"0
4
$oise Immunit"
%''ect o' input noise o' gate operation
5
$oise Immunit"
%''ect o' input noise o' gate operation
6
$oise Margin

! measure o' a circuit noise immunit" is called

the noise margin3 *hich is e7pressed in (olts0

There are t*o (alues o' noise margin speci'ied

'or the gi(en logic circuit8 the 9I9-le(el noise
margin .:$9/ and the LO;-le(el noise margin
.:$L/0
q
:$9 < :O9.min/ = :I9.min/
q
:$L < :IL.ma7/ = :OL.ma7/
>
$oise Margin
1?
11
#ropagation Dela"

#ropagation dela"3 is the time re2uired 'or a digital

signal to tra(el 'rom the input.s/ o' a logic gate to the
output0

I' the output o' alogic gateis connected to a long

trace or used to dri(e man" othergates.highfanout/
the propagation dela" increases su-stantiall"0
12
#ropagation Dela"

There are t*o propagation dela" time

speci'ied 'or logic gates0
1/ t#9L8 #ropagation Dela" Time 'rom 9I9 to LO;0
2/ t#L98 #ropagation Dela" Time 'rom LO; to 9I9
1+
Fan In ) Fan Out

Fan-inis the num-er o' inputs a gate can handle0

The 'an-in de'ined as the ma7imum num-er o' inputs

that a logic gate can accept0

I' num-er o' input e7ceeds3 the output *ill -e

unde'ined or incorrect0 It is speci'ied -"
manu'acturer and is pro(ided in the data sheet0
1,
Fan-In ) Fan-Out

The 'an-out is de'ined as the ma7imum num-er o'

inputs .load/ that can -e connected to the output o'
a gate *ithout degrading the normal operation0

Fan Out is calculated 'rom the amount o' current

a(aila-le in the output o' a gate and the amount o'
current needed in each input o' the connecting gate0
It is speci'ied -" manu'acturer and is pro(ided in the
data sheet0

%7ceeding the speci'ied ma7imum load ma" cause a

mal'unction -ecause the circuit *ill not -e a-le
suppl" the demanded po*er0 15
Fan-In ) Fan-Out
14
#o*er Dissipation

!s po*er is de'ined as the rate o' energ"

trans'er3 @po*er dissipation@ is a measure o'
the rate at *hich energ" is dissipated3 or lost3
'rom an electrical s"stem0

! logic gate dra*s current 'rom the dc suppl"

(oltage source indicated in ne7t slide 'igure0

;hen the gate is in the 9I9 output state3 an

amount o' current designated -" ICC9 is
dra*n3 and in the LO; output state3 a
di''erent amount o' current ICCL is dra*n
15
#o*er Dissipation
16
#o*er Dissipation

%7ample8 I' ICC9 is speci'ied as 105m! *hen

:CC is 5: and i' the gate is in a static
.nonchanging/ 9I9 output state3 the po*er
dissipation .#D/ o' the gate is
#D < :CCAICC9 < .5:/ A .105 m!/ < 505 m;
1>
#o*er Dissipation

;hen a gate is pulsed3 its output s*itches

-acB and 'orth -et*een 9I9 and LO;3 and
the amount o' suppl" current (aries -et*een
ICC9 and ICCL0

The a(erage po*er dissipation depends on the

dut" c"cle and is usuall" speci'ied 'or a dut"
c"cle o' 5?C0

;hen the dut" c"cle is 5?C the output is 9I9

hal' the time and LO; the other hal'0 The
a(erage suppl" current is there'ore
2?
#o*er Dissipation

The a(erage suppl" current is there'ore

The a(erage po*er dissipation is

#D < :CCAICC9

21
22
Dela" #o*er #roduct

Indigital electronics3 thepo*er=dela"

productis a 'igure o' merit correlated *ith the
energ" e''icienc" o' a logic gate orlogic 'amil"0

!lso Bno*n ass*itching energ"3 it is the

product o' po*er consumption .a(eraged o(er
a s*itching e(ent/ times the input=output
dela"3 or duration o' the s*itching e(ent0

It has the dimension o' energ"3 and measures

the energ" consumed per s*itching e(ent0
2+
Dela" #o*er #roduct

So3 an ideal digital technolog" *ould ha(e

(er" small propagation dela" tp3 and (er"
small
po*er dissipation #D0

But3 there is a pro-lem0 Designing aD'asterE

.e0g03 lo*er tp/ digital gate usuall" re2uires
greater power0 !nd designing a gate to
minimiFe po*er consumption usuall" slows
down the digital de(ice0

#ropagation dela" and po*er dissipation

generall" 'orm a design trade off - impro(e
one and "ou degrade the other
2,
Dela" #o*er #roduct

The merit o' comparing logic-circuit

technologies .or 'amilies/ is the dela" po*er
product de'ined as
D# < #D tp

;here #D is the po*er dissipation o' the gate0

$ote that D# has the units o' Goules0
25
Silicon !rea

The design o' digital :LSI circuits is the

minimiFation o' silicon area per logic gate0

Smaller area re2uirement ena-les the

'a-rication o' a larger num-er o' gates per chip0

Area reduction occurs in three different ways:

10 Through ad(ances in processing technolog"
that ena-les the reduction o' the minimum
de(ice siFe
20 Through ad(ances in circuit design techni2ues0
20 Through care'ul chip la"out0

eneral rule3 the simpler the circuit3 the smaller

the area re2uired0
24
%nd o' Lecture-2-5
25