Discrete Event Simulation

Homework 1
Homework 1: Provided Materials
Material/Simulator:
• run.py: python script to run event driven simulation (see lectures 6)
• supporting python scripts

Material/ISCAS:
• cXXX.bench: ISCAS 85 benchmark circuit netlist
• add_inputs.py: python script to add input vectors for simulation

Material/Projects:
• projectX.ipynb: jupyter notebook to collect your deliverables

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Project 1: Switching Activity Levels
Modify the logic simulator to:
a) For each input port individually, specify the input signal waveform
by an “activity level” from 0.0 (not switching at all) to 100.0
(switching at every cycle).
INPUT(G1gat,0.113)

b) Add analysis code to measure the activity level of the outputs of

the circuit on the same scale as above (0-100).

c) Run three of the ISCAS benchmarks for inputs switching at (the

same rate of) 1%, 2%, 3%, 5%, 10%, 20% and measure the activity
level of the outputs.

d) Plot the circuit output vs. input switching levels.

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Project 1: Creating Activity
• Activity level defines the average number of times that an input
switches within a given number of “cycles”

• It is an average because within a specific time window, a signal may

have a different activity

• The input needs to be random, so ---S---S---S---S---S… is not

acceptable for a 25% activity input waveform
• Here we denote a cycle without switching with a – and a cycle with switching
with a S

• Hint: think of each cycle as a random number from 0 to 100, and if

the number is less than the activity then you switch, otherwise not
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Project 1: Measuring Activity
• We have an output signal as a sequence of 0 and 1 values

• We need to count the number of times that the signal changed

• With that, the activity is simply (# changes)/(length of signal)

• Circuit activity (CA) = average activity across all the outputs

• Hint: XOR

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Project 1: Test Circuits
Circuit Inputs Outputs Gates
C17 5 2 6 For debugging only
C432 36 7 127
C499 41 32 386
C880 60 26 306
C1355 41 32 390
C1908 33 25 354
C2670 233 139 534
C3540 50 22 918
C5315 178 123 1323
C6288 32 32 1870
C7552 207 108 1377

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Project 1: Deliverables
1. Showing your modifications:
1.1. Give a high level explanation of how your code works (modification a – d)
and how you ran the simulations.

For each of the 3 (or more) benchmark circuits perform simulations with
input waveforms of 1000 cycles:
1.2. Table of CA vs. input activity of 1, 2, 3, 5, 10 and 20%
1.3. A plot of CA vs. input activity per circuit
1.4. A boxplot of output activity at all outputs vs. input activity
1.5. Comment on the relationship between the input and the resulting activity

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Project 1: Deliverables
2. Exploration of the number of cycles:
Create 100 input waveforms with activity of 1, 3, 10 and 30% and with
lengths of 1000 cycles for one ISCAS circuit.
Measure the CA of the 100 waveforms.
2.1. Make a plot of the measured CA vs. intended activity for each
1st 10, 1st 100 and all 1000 cycles

Create 100 single waveforms with activity of 1, 3, 10 and 30% and with length
of 1000 cycles.
2.2. Taking the 1st N of the 1000 cycles and measuring the activity within them for
each of the 100 waveforms, make a plot of the activity in those 100 waveforms
vs. N (see next page for example)

Determine the length at which the input activity is within 10% of the
target activity.
2.3. Make a plot of that length vs. activity level
2.4. Comment on any observations for task 2

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 Activity Plot
observed / desired level of activity
100

10

log scale
N
1 log scale 10 100 1000
1

0.1

0.01
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Project 2: Multiple Delay Simulation
Modify the logic simulator to:
a) Allow the delay of a gate to be something other than = 1
b) Add a “size” and an intrinsic delay for each gate, which can be any
positive number
c) Make the delay of a gate be proportional to the sum of the intrinsic delay
and the sum of sizes of all its fanout gates divided by the size of the gate
d) Add analysis code to find the time it takes the latest output to
change (this is the “maximum delay”)

e) Run three of the ISCAS benchmarks for 1000 unique input patterns
each, collect the maximum delay for each unique input pattern,
plot and comment on the distribution of maximum delays
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Project 2: Size and Delay
• Each gate needs a size which is a positive real number
• 0.1, 20.0, 0.5 etc.

• The delay of a gate is the difference between the time of the input
event and the time of the resulting output event
• This also means that the event time is no longer an integer

Gate1=S1
Gate Gate0
S0 Gate2=S2
output
input

D0
Gate3=S3
time
delay = D0 + (S1+S2+S3)/S0
delay

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Project 2: Maximum Delay
• All inputs switch at the same time, and then remain constant

• Outputs may or may not switch

• Maximum delay is the latest of the outputs

Circuit

all inputs

output
output
output
output
output
output
Circuit
time
maximum delay

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Project 2: Test Circuits
Circuit Inputs Outputs Gates
C17 5 2 6 For debugging only
C432 36 7 127
C499 41 32 386
C880 60 26 306
C1355 41 32 390
C1908 33 25 354
C2670 233 139 534
C3540 50 22 918
C5315 178 123 1323
C6288 32 32 1870
C7552 207 108 1377

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Project 2: Deliverables
1. Showing your modification:
For each of 3 test circuits, generate 1000 inputs (each input is one transition
on a random subset of the inputs)
1.1. A high level description of how you generated the 1000 inputs and how
your code of the modifications a – d works

For each of 3 tests circuits, simulate and find the maximum delay for each of
the 1000 inputs
1.2. A high level description of how you performed the simulation
1.3. A histogram of the 1000 values of maximum delay
1.4. A comment on the shape of the histogram

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Project 2: Deliverables
2. Considering your maximum delay calculation:
Pick one of the three circuits you analyzed.
Pick one of the input pattern that resulted in the maximum delay.

Find the gate G* in the circuit which is the most important in determining
the maximum delay
(hint: find the sensitivity of the maximum delay to each gate size)
2.1. A high level description of how your code to determine G* works
2.2. Make a plot of the maximum delay vs. the size of the G*
2.3. Comment on any observations

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Homework 1: Procedure
1. Team Selection:
- teams up to 4 members
- all members register for their selected team (A-Z) on moodle

2. Homework Hand-In:
- Materials are published there
- One member uploads deliverables for whole team
- you can choose ONE project
- Working period: 12.05., 9:00 – 28.05., 23:59 (hard deadline)

3. Presentation Slot Reservation:

- 20 min discussion about results (all members have to contribute)
- timeslots can be booked online, one member reserves for whole team
- slots will be added later (probably for week from 30.05.)
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Homework 1: Questions

Questions are only answered via Homework forum on Moodle!

And of course now.

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