BAB17 - The Additional Discrete Library

Chapter 17
The Additional Discrete Library
his chapter is an introduction to the Additional Discrete Library. This is the sixteenth
library in the Simulink group of libraries and contains the blocks shown below. We will
describe the function of each block included in this library and we will perform simulation
examples to illustrate their application.
Introduction to Simulink with Engineering Applications

Copyright Orchard Publications
171
Chapter 17 The Additional Discrete Library

17.1 The Transfer Fcn Direct Form II Block
The Transfer Fcn Direct Form II block implements a Direct Form II realization of the transfer
function specified by the Numerator coefficients and the Denominator coefficients without the
leading* coefficient in the Denominator.
Example 17.1
The model of Figure 17.1 implements the discretetime function
1
0.5276 1.5828z + 1.5828z H ( z ) = --------------------------------------------------------------------------1

2
1 1.7600z + 1.1829z
(17.1)
Figure 17.1. Direct FormII of a second-order digital filter
In Figure 17.1, the Sample time for the Sine Wave block is specified as 0.1. The num ( z ) for the
Transfer Fcn Direct Form II block is specified as [ 0.5276 1.5828 1.5828 ] , and the den ( z ) is
specified as [ 1.7600 1.1829 ] . The leading coefficient 1 in the denominator is excluded. The
input and output waveforms are shown in Figure 17.2.
* By lead we mean that the leading coefficient 1 in the denominator which has the form 1 + z1 + z 2 .
172

The Transfer Fcn Direct Form II Time Varying Block
Figure 17.2. Input and output waveforms for the model of Figure 17.1
17.2 The Transfer Fcn Direct Form II Time Varying Block
The Transfer Fcn Direct Form II Time Varying block implements a Direct Form II realization
of a specified transfer function. Essentially, this block performs the same function as that of the
Transfer Fcn Direct Form II block which is described in the previous section, except that the
numerator and denominator coefficients of the discretetime transfer function are specified externally by two inputs Num and Den.
Example 17.2
The model of Figure 17.3 is essentially the same as that of Figure 17.1 and thus the input and output waveforms of Figure 17.4 are the same as those of Figure 17.2.

173
Figure 17.3. Model for Example 17.3
17.3 The FixedPoint StateSpace Block
The FixedPoint StateSpace block implements the system described by

x [ n + 1 ] = Ax [ n ] + Bu [ n ]
y [ n ] = Cx [ n ] + Du [ n ]
(17.2)
where:
A is a matrix with dimensions n n , n = number of states , B is a matrix with dimensions
n m , m = number of inputs , C is a matrix with dimensions r n , r = number of outputs , D
174

The FixedPoint StateSpace Block

is a matrix with dimensions r m , x = state, an n 1 vector , u = input, an m 1 vector , and
y = output, an r 1 vector .
Example 17.3
The matrix form of a 3input 2output 3state discretetime system is specified as
x2 [ n + 1 ] =
x1 [ n ]
x2 [ n ] +
x3 [ n + 1 ]
0.25
0
0
0
0.5
0
0 0.25 0.75
x3 [ n ]
0 1 0
0 0 1
1 0 1
x1 [ n + 1 ]
A
=
y2 [ n ]
1 0 1
0 1 0
x1 [ n ]
0 1 0
0 0 1
x2 [ n ] +
x3 [ n ]
y1 [ n ]
u1 [ n ]
u2 [ n ]
u3 [ n ]
(17.3)
u1 [ n ]
u2 [ n ]
u3 [ n ]
In the model of Figure 17.5 we enter the values of matrices A, B, C, and D in the FixedPoint
StateSpace block parameters dialog box, and we specify initial condition 0. The input vector is as
shown and when the simulation command is given the input and output waveforms are as shown
in Figure 17.6.

175
17.4 The Unit Delay External IC Block
The Unit Delay External IC (Initial Condition) block delays its input by one sample period. This
block is equivalent to the z 1 discretetime operator. The block accepts one input and generates
one output, both of which can be scalar or vector. If the input is a vector, all elements of the vector are delayed by the same sample period. The block's output for the first sample period is equal
to the signal IC. The input u and initial condition IC data types must be the same.
Example 17.4
In the model of Figure 17.7, the Pulse Generator block is specified for a period 2 sec. All other
parameters are in their default state. The input and output waveforms are shown in Figure 17.8.
176

The Unit Delay Resettable Block
17.5 The Unit Delay Resettable Block
The Unit Delay Resettable block delays a signal one sample period. If the reset input signal is
false, the block outputs the input signal delayed by one time step. If the reset signal is true, the
block resets the current state to the initial condition, specified by the Initial condition parameter,
and outputs that state delayed by one time step.
Example 17.5
In the model of Figure 17.9, the Pulse Generator 1 block is specified for a period 2 sec. and the
Pulse Generator 2 block is set for a period 4 sec. All other parameters are in their default state.
The input and output waveforms are shown in Figure 17.10.

177
17.6
The Unit Delay Resettable External IC Block
The Unit Delay Resettable External IC block delays a signal one sample period. The block can
be reset by the external reset signal R. The block has two input ports, one for the input signal u
and the other for the reset signal R. When the reset signal is false, the block outputs the input signal delayed by one time step. When the reset signal is true, the block resets the current state to
the initial condition given by the signal IC and outputs that state delayed by one time step.
Example 17.6
In the model of Figure 17.11, the Pulse Generator 1 block is set for a period 2 sec. and the Pulse
Generator 2 block is set for a period 4 sec. All other parameters are in their default state. The
input and output waveforms are shown in Figure 17.12.
178

The Unit Delay Enabled Block
17.7 The Unit Delay Enabled Block
The Unit Delay Enabled block delays a signal by one sample period when the external enable signal E is on. When the enable signal E is off, the block is disabled. The block holds the current
state at the same value and outputs that value. The enable signal is on when E is not 0, and is off
when E is 0.

179

Example 17.7
Figure 17.13 contains two models where in the upper model the Unit Delay Enabled 1 block is
disabled and thus its output is zero. In the lower model the Unit Delay Enabled 2 block is enabled
and causes a delay in the input signal before being propagated to the Discrete Time Integrator
Forward Euler 2 block. The inputs and outputs are shown in Figure 17.14.
Figure 17.13. Models for Example 17.7
Figure 17.14. Input and Output waveforms for the models of Figure 17.7
1710

The Unit Delay Enabled Resettable Block

17.8 The Unit Delay Enabled Resettable Block
The Unit Delay Enabled Resettable block delays a signal one sample period, if the external
enable signal is on. This block combines the features of the Unit Delay Enabled and Unit Delay
Resettable blocks. When the enable signal E is on and the reset signal R is false, the block outputs
the input signal delayed by one sample period. When the enable signal E is on and the reset signal
R is true, the block resets the current state to the initial condition, specified by the Initial condition parameter, and outputs that state delayed by one sample period. When the enable signal is
off, the block is disabled, and the state and output do not change except for resets. The enable signal is on when E is not 0, and off when E is 0.
Example 17.8
In the model of Figure 17.15, the Pulse Generator 1 block is specified for a period 2 sec., the Pulse
Generator 2 block is specified for a period 3 sec., and the Pulse Generator 3 block is specified for a
period 4 sec. All other parameters are in their default state. The input and output waveforms are
shown in Figure 17.16.

1711
17.9 The Unit Delay Enabled External IC Block
The Unit Delay Enabled External IC block delays a signal by one sample period when the enable
signal E is on. When the enable is off, the block holds the current state at the same value and outputs that value. The enable E is on when E is not 0, and off when E is 0. The initial condition of
this block is specified by the input signal IC. Essentially, this block is the same as the Unit Delay
Enabled block which we described in the previous section of this chapter except that the initial
condition is specified by an external block.
Example 17.9
In the model of Figure 17.17, the Constant 1 block enables the Unit Delay Enabled External IC
block while the Constant 2 block is set to 1 to specify the initial condition. The input and output
waveforms are shown in Figure 17.18.
1712

The Unit Delay Enabled Resettable External IC Block
17.10 The Unit Delay Enabled Resettable External IC Block
The Unit Delay Enabled Resettable External IC block is a combination of the functions performed by the Unit Delay Enabled, Unit Delay External IC, and Unit Delay Resettable blocks.
The block can reset its state based on an external reset signal R. When the enable signal E is on
and the reset signal R is false, the block outputs the input signal delayed by one sample period.
When the enable signal E is on and the reset signal R is true, the block resets the current state to
the initial condition given by the signal IC, and outputs that state delayed by one sample period.
When the enable signal is off, the block is disabled, and the state and output do not change
except for resets. The enable signal is on when E is not 0, and off when E is 0.
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Example 17.10
In the model of Figure 17.19, the Pulse Generator 1 block is specified for a period 2 sec., the Pulse
Generator 2 block is specified for a period 3 sec., and the Pulse Generator 3 block is specified for a
period 4 sec. All other parameters are in their default state. The input and output waveforms are
1714

The Unit Delay With Preview Resettable Block

17.11 The Unit Delay With Preview Resettable Block
The Unit Delay With Preview Resettable block can reset its state based on an external reset signal R. The block has two output ports. When the reset R is false, the upper port outputs the signal
and the lower port outputs the signal delayed by one sample period. When the reset R is true, the
block resets the current state to the initial condition given by the Initial condition parameter. The
block outputs that state delayed by one sample time through the lower output port, and outputs
the state without a delay through the upper output port.
Example 17.11
In the model of Figure 17.21, the Pulse Generator 1 block is specified for a period 2 sec. and the
Pulse Generator 2 block is specified for a period 4 sec. All other parameters are in their default
state. The input and output waveforms are shown in Figure 17.22.

1715
Figure 17.22. Waveforms for the model of Figure 17.21
17.12 The Unit Delay With Preview Resettable External RV Block
The Unit Delay With Preview Resettable External RV block has three input and two output
ports. This block can reset its state based on the state of the an external input reset signal R.
When the external reset R is false, the upper port outputs the signal and the lower port outputs
the signal delayed by one sample period. When the external reset R is true, the upper output signal is forced to equal the external input reset signal RV. The lower output signal is not affected
until one time step later, at which time it is equal to the external reset signal RV at the previous
time step. The block uses the internal Initial condition only when the model starts or when a parent enabled subsystem is used. The internal Initial condition only affects the lower output signal.
Example 17.12
In the model of Figure 17.23, the Pulse Generator 1, 2, and 3 blocks are specified for the periods
shown on the model. All other parameters are in their default state. The input and output waveforms are shown in Figure 17.24.
1716

The Unit Delay With Preview Enabled Block
17.13 The Unit Delay With Preview Enabled Block
The Unit Delay With Preview Enabled block has two input and two output ports. When the
external input enable signal E is on, the upper port outputs the signal and the lower port outputs

1717

the signal delayed by one sample period. When the enable signal E is off, the block is disabled, and
the state and output values do not change. The enable signal is on when E is not 0, and off when
E is 0.
Example 17.13
In the model of Figure 17.25, the Pulse Generator block is set for a period 2 sec. All other parameters are in their default state. The input and output waveforms are shown in Figure 17.26.
1718

The Unit Delay With Preview Enabled Resettable Block

17.14 The Unit Delay With Preview Enabled Resettable Block
The Unit Delay With Preview Enabled Resettable block has three inputs and two outputs. This
block can reset its state based on an external input reset signal R. When the external enable signal E is on and the reset R is false, the upper port outputs the signal and the lower port outputs
the signal delayed by one sample period. When the enable input signal E is on and the reset R is
true, the block resets the current state to the initial condition given by the Initial condition
parameter. The block outputs that state delayed by one sample time through the lower output
port, and outputs the state without a delay through the upper output port. When the Enable signal is off, the block is disabled, and the state and output values do not change, except for resets.
The enable signal is on when E is not 0, and off when E is 0.
Example 17.14
In the model of Figure 17.27, the Pulse Generator 1, 2, and 3 blocks are specified for the period
shown on the model. All other parameters are in their default state. The input and output waveforms are shown in Figure 17.28.

1719
17.15 The Unit Delay With Preview Enabled Resettable External RV Block
The Unit Delay With Preview Enabled Resettable External RV block has four inputs and two
outputs. This block can reset its state based on an external reset signal R. When the external
enable signal E is on and the reset R is false, the upper port outputs the signal and the lower port
outputs the signal delayed by one sample period.
When the enable signal E is on and the reset R is true, the upper output signal is forced to equal
the external input reset signal RV. The lower output signal is not affected until one time step
later, at which time it is equal to the external reset signal RV at the previous time step. The block
uses the internal Initial condition only when the model starts or when a parent enabled subsystem
is used. The internal Initial condition only affects the lower output signal. When the Enable signal
is off, the block is disabled, and the state and output values do not change, except for resets. The
enable signal is on when E is not 0, and off when E is 0.
1720

The Unit Delay With Preview Enabled Resettable External RV Block

Example 17.15
In the model of Figure 17.29, the Pulse Generator 1, 2, and 3 blocks are set for the periods shown
on the model. All other parameters are in their default state. The input and output waveforms are

1721

17.16 Summary
The Transfer Fcn Direct Form II block implements a Direct Form II realization of the transfer function specified by the Numerator coefficients and the Denominator coefficients without
the leading coefficient in the Denominator.
The Transfer Fcn Direct Form II Time Varying block implements a Direct Form II realization of a specified transfer function. Essentially, this block performs the same function as that
of the Transfer Fcn Direct Form II block.
The FixedPoint StateSpace block implements the system described by
x [ n + 1 ] = Ax [ n ] + Bu [ n ]
y [ n ] = Cx [ n ] + Du [ n ]
The Unit Delay External IC (Initial Condition) block delays its input by one sample period.
This block is equivalent to the z 1 discrete-time operator. The block accepts one input and
generates one output, both of which can be scalar or vector. If the input is a vector, all elements of the vector are delayed by the same sample period. The block's output for the first
sample period is equal to the signal IC. The input u and initial condition IC data types must be
the same.
The Unit Delay Resettable block delays a signal one sample period. If the reset input signal is
false, the block outputs the input signal delayed by one time step. If the reset signal is true, the
block resets the current state to the initial condition, specified by the Initial condition parameter, and outputs that state delayed by one time step.
The Unit Delay Resettable External IC block delays a signal one sample period. The block
can be reset by the external reset signal R. The block has two input ports, one for the input signal u and the other for the reset signal R. When the reset signal is false, the block outputs the
input signal delayed by one time step. When the reset signal is true, the block resets the current
state to the initial condition given by the signal IC and outputs that state delayed by one time
step.
The Unit Delay Enabled block delays a signal by one sample period when the external enable
signal E is on. When the enable signal E is off, the block is disabled. The block holds the current state at the same value and outputs that value. The enable signal is on when E is not 0,
and is off when E is 0.
The Unit Delay Enabled Resettable block delays a signal one sample period, if the external
enable signal is on. This block combines the features of the Unit Delay Enabled and Unit Delay
Resettable blocks.
The Unit Delay Enabled External IC block delays a signal by one sample period when the
enable signal E is on. When the enable is off, the block holds the current state at the same
1722

Summary
value and outputs that value. The enable E is on when E is not 0, and off when E is 0. The initial condition of this block is specified by the input signal IC.
The Unit Delay Enabled Resettable External IC block is a combination of the functions performed by the Unit Delay Enabled, Unit Delay External IC, and Unit Delay Resettable blocks.
The Unit Delay With Preview Resettable block has two input and two output ports. This
block can reset its state based on the state of the external input reset signal R. When the reset
R is false, the upper port outputs the signal and the lower port outputs the signal delayed by
one sample period. When the reset R is true, the block resets the current state to the initial
condition given by the Initial condition parameter. The block outputs that state delayed by
one sample time through the lower output port, and outputs the state without a delay through
the upper output port.
The Unit Delay With Preview Resettable External RV block has three input and two output
ports. This block can reset its state based on the state of the an external input reset signal R.
When the external reset R is false, the upper port outputs the signal and the lower port outputs
the signal delayed by one sample period. When the external reset R is true, the upper output
signal is forced to equal the external input reset signal RV. The lower output signal is not
affected until one time step later, at which time it is equal to the external reset signal RV at the
previous time step. The block uses the internal Initial condition only when the model starts or
when a parent enabled subsystem is used. The internal Initial condition only affects the lower
output signal.
The Unit Delay With Preview Enabled block has two input and two output ports. When the
external input enable signal E is on, the upper port outputs the signal and the lower port outputs the signal delayed by one sample period. When the enable signal E is off, the block is disabled, and the state and output values do not change. The enable signal is on when E is not 0,
and off when E is 0.
The Unit Delay With Preview Enabled Resettable block has three inputs and two outputs.
This block can reset its state based on an external input reset signal R. When the external
enable signal E is on and the reset R is false, the upper port outputs the signal and the lower
port outputs the signal delayed by one sample period. When the enable input signal E is on and
the reset R is true, the block resets the current state to the initial condition given by the Initial
condition parameter. The block outputs that state delayed by one sample time through the
lower output port, and outputs the state without a delay through the upper output port. When
the Enable signal is off, the block is disabled, and the state and output values do not change,
except for resets. The enable signal is on when E is not 0, and off when E is 0.
The Unit Delay With Preview Enabled Resettable External RV block has four inputs and
two outputs. This block can reset its state based on an external reset signal R. When the external enable signal E is on and the reset R is false, the upper port outputs the signal and the lower
port outputs the signal delayed by one sample period. When the enable signal E is on and the

1723

reset R is true, the upper output signal is forced to equal the external input reset signal RV.
The lower output signal is not affected until one time step later.
1724


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Chapter 17

The Additional Discrete Library

Introduction to Simulink with Engineering Applications

Chapter 17 The Additional Discrete Library

0.5276 1.5828z + 1.5828z H ( z ) = --------------------------------------------------------------------------1

Figure 17.1. Direct FormII of a second-order digital filter

Introduction to Simulink with Engineering Applications

The Transfer Fcn Direct Form II Time Varying Block

17.2 The Transfer Fcn Direct Form II Time Varying Block

Introduction to Simulink with Engineering Applications

Chapter 17 The Additional Discrete Library

Figure 17.3. Model for Example 17.3

17.3 The FixedPoint StateSpace Block

The FixedPoint StateSpace block implements the system described by

Introduction to Simulink with Engineering Applications

The FixedPoint StateSpace Block

Figure 17.5. Model for Example 17.3

Introduction to Simulink with Engineering Applications

Chapter 17 The Additional Discrete Library

17.4 The Unit Delay External IC Block

Figure 17.7. Model for Example 17.4

Introduction to Simulink with Engineering Applications

The Unit Delay Resettable Block

17.5 The Unit Delay Resettable Block

Figure 17.9. Model for Example 17.5

Introduction to Simulink with Engineering Applications

Chapter 17 The Additional Discrete Library

The Unit Delay Resettable External IC Block

Introduction to Simulink with Engineering Applications

The Unit Delay Enabled Block

Figure 17.11. Model for Example 17.6

17.7 The Unit Delay Enabled Block

Introduction to Simulink with Engineering Applications

Chapter 17 The Additional Discrete Library

Figure 17.13. Models for Example 17.7

Introduction to Simulink with Engineering Applications

The Unit Delay Enabled Resettable Block

Figure 17.15. Model for Example 17.8

Introduction to Simulink with Engineering Applications

Chapter 17 The Additional Discrete Library

17.9 The Unit Delay Enabled External IC Block

Introduction to Simulink with Engineering Applications

The Unit Delay Enabled Resettable External IC Block

Figure 17.17. Model for Example 17.9

17.10 The Unit Delay Enabled Resettable External IC Block

Chapter 17 The Additional Discrete Library

Figure 17.19. Model for Example 17.10

Introduction to Simulink with Engineering Applications

The Unit Delay With Preview Resettable Block

Figure 17.21. Model for Example 17.11

Introduction to Simulink with Engineering Applications

Chapter 17 The Additional Discrete Library

Figure 17.22. Waveforms for the model of Figure 17.21

17.12 The Unit Delay With Preview Resettable External RV Block

Introduction to Simulink with Engineering Applications

The Unit Delay With Preview Enabled Block

Figure 17.23. Model for Example 17.12

Figure 17.24. Waveforms for the model of Figure 17.23

17.13 The Unit Delay With Preview Enabled Block

Introduction to Simulink with Engineering Applications

Chapter 17 The Additional Discrete Library

Figure 17.25. Model for Example 17.13

Figure 17.26. Waveforms for the model of Figure 17.25

Introduction to Simulink with Engineering Applications