CMOSinterviewquestions.

1/Whatislatchup?
Latchuppertainstoafailuremechanismwhereinaparasiticthyristor(suchasaparasitic
siliconcontrolledrectifier,orSCR)isinadvertentlycreatedwithinacircuit,causingahigh
amountofcurrenttocontinuouslyflowthroughitonceitisaccidentallytriggeredorturned
on.Dependingonthecircuitsinvolved,theamountofcurrentflowproducedbythis
mechanismcanbelargeenoughtoresultinpermanentdestructionofthedevicedueto
electricaloverstress(EOS)
2)WhyisNANDgatepreferredoverNORgateforfabrication?
NANDisabettergatefordesignthanNORbecauseatthetransistorlevelthemobilityof
electronsisnormallythreetimesthatofholescomparedtoNORandthustheNANDisa
fastergate.
Additionally,thegateleakageinNANDstructuresismuchlower.Ifyouconsidert_phland
t_plhdelaysyouwillfindthatitismoresymmetricincaseofNAND(thedelayprofile),but
forNOR,onedelayismuchhigherthantheother(obviouslyt_plhishighersincethehigher
resistancepmos'sareinseriesconnectionwhichagainincreasestheresistance).
3)WhatisNoiseMargin?ExplaintheproceduretodetermineNoiseMargin
Theminimumamountofnoisethatcanbeallowedontheinputstageforwhichtheoutput
willnotbeeffected.
4)Explainsizingoftheinverter?
Inordertodrivethedesiredloadcapacitancewehavetoincreasethesize(width)ofthe
inverterstogetanoptimizedperformance.
5)HowdoyousizeNMOSandPMOStransistorstoincreasethethresholdvoltage?
6)WhatisNoiseMargin?ExplaintheproceduretodetermineNoiseMargin?
Theminimumamountofnoisethatcanbeallowedontheinputstageforwhichtheoutput
willnotbeeffected.
7)Whathappenstodelayifyouincreaseloadcapacitance?
delayincreases.
8)WhathappenstodelayifweincludearesistanceattheoutputofaCMOScircuit?
Increases.(RCdelay)
9)Whatarethelimitationsinincreasingthepowersupplytoreducedelay?
Thedelaycanbereducedbyincreasingthepowersupplybutifwedosotheheatingeffect
comesbecauseofexcessivepower,tocompensatethiswehavetoincreasethediesizewhich
isnotpractical.

10)HowdoesResistanceofthemetallinesvarywithincreasingthicknessandincreasing
length?
R=(*l)/A.
11)ForCMOSlogic,givethevarioustechniquesyouknowtominimizepowerconsumption?
Powerdissipation=CV2f,fromthisminimizetheloadcapacitance,dcvoltageandthe
operatingfrequency.
12)WhatisChargeSharing?ExplaintheChargeSharingproblemwhilesamplingdatafrom
aBus?
IntheseriallyconnectedNMOSlogictheinputcapacitanceofeachgatesharesthecharge
withtheloadcapacitancebywhichthelogicallevelsdrasticallymismatchedthanthatofthe
desiredonce.Toeliminatethisloadcapacitancemustbeveryhighcomparedtotheinput
capacitanceofthegates(approximately10times).
13)Whydowegraduallyincreasethesizeofinvertersinbufferdesign?Whynotgivethe
outputofacircuittoonelargeinverter?
Becauseitcannotdrivetheoutputloadstraightaway,sowegraduallyincreasethesizetoget
anoptimizedperformance.
14)WhatisLatchUp?ExplainLatchUpwithcrosssectionofaCMOSInverter.Howdoyou
avoidLatchUp?
LatchupisaconditioninwhichtheparasiticcomponentsgiverisetotheEstablishmentof
lowresistanceconductingpathbetweenVDDandVSSwithDisastrousresults.
15)GivetheexpressionforCMOSswitchingpowerdissipation?
CV2
16)WhatisBodyEffect?
IngeneralmultipleMOSdevicesaremadeonacommonsubstrate.Asaresult,thesubstrate
voltageofalldevicesisnormallyequal.Howeverwhileconnectingthedevicesseriallythis
mayresultinanincreaseinsourcetosubstratevoltageasweproceedverticallyalongthe
serieschain(Vsb1=0,Vsb20).WhichresultsVth2>Vth1.
17)WhyisthesubstrateinNMOSconnectedtoGroundandinPMOStoVDD?
wetrytoreversebiasnotthechannelandthesubstratebutwetrytomaintainthedrain,source
junctionsreversebiasedwithrespecttothesubstratesothatwedontlooseourcurrentinto
thesubstrate.
18)WhatisthefundamentaldifferencebetweenaMOSFETandBJT?
InMOSFET,currentflowiseitherduetoelectrons(nchannelMOS)orduetoholes(p
channelMOS)InBJT,weseecurrentduetoboththecarriers..electronsandholes.BJTisa
currentcontrolleddeviceandMOSFETisavoltagecontrolleddevice.

19)Whichtransistorhashighergain.BJTorMOSandwhy?
BJThashighergainbecauseithashighertransconductance.Thisisbecausethecurrentin
BJTisexponentiallydependentoninputwhereasinMOSFETitissquarelaw.
20)Whydowegraduallyincreasethesizeofinvertersinbufferdesignwhentryingtodrivea
highcapacitiveload?Whynotgivetheoutputofacircuittoonelargeinverter?
Wecannotuseabiginvertertodrivealargeoutputcapacitancebecause,whowilldrivethe
biginverter?Thesignalthathastodrivetheoutputcapwillnowseealargergatecapacitance
oftheBIGinverter.Sothisresultsinslowraiseorfalltimes.Aunitinvertercandrive
approximatelyaninverterthats4timesbiggerinsize.Sosayweneedtodriveacapof64
unitinverterthenwetrytokeepthesizinglikesay1,4,16,64sothateachinverterseesasame
ratioofoutputtoinputcap.Thisistheprimereasonbehindgoingforprogressivesizing.
21)InCMOStechnology,indigitaldesign,whydowedesignthesizeofpmostobehigher
thanthenmos.Whatdeterminesthesizeofpmoswrtnmos.Thoughthisisasimplequestion
trytolistallthereasonspossible?
InPMOSthecarriersareholeswhosemobilityisless[aprroxhalf]thantheelectrons,the
carriersinNMOS.ThatmeansPMOSisslowerthananNMOS.InCMOStechnology,nmos
helpsinpullingdowntheoutputtogroundannPMOShelpsinpullinguptheoutputtoVdd.
IfthesizesofPMOSandNMOSarethesame,thenPMOStakeslongtimetochargeupthe
outputnode.IfwehavealargerPMOSthantherewillbemorecarrierstochargethenode
quicklyandovercometheslownatureofPMOS.Basicallywedoallthistogetequalrise
andfalltimesfortheoutputnode.
22)WhyPMOSandNMOSaresizedequallyinaTransmissionGates?
InTransmissionGate,PMOSandNMOSaideachotherrathercompetingwitheachother.
That'sthereasonwhyweneednotsizethemlikeinCMOS.InCMOSdesignwehave
NMOSandPMOScompetingwhichisthereasonwetrytosizethemproportionaltotheir
mobility.
23)Allofusknowhowaninverterworks.WhathappenswhenthePMOSandNMOSare
interchangedwithoneanotherinaninverter?
IhaveseensimilarQsinsomeofthediscussions.Ifthesource&drainalsoconnected
properly...itactsasabuffer.Butsupposeinputislogic1O/Pwillbedegraded1Similarly
degraded0;
24)AgoodquestiononLayouts.Give5importantDesigntechniquesyouwouldfollowwhen
doingaLayoutforDigitalCircuits?
a)Indigitaldesign,decidetheheightofstandardcellsyouwanttolayout.Itdependsupon
howbigyourtransistorswillbe.HavereasonablewidthforVDDandGNDmetal
paths.MaintaininguniformHeightforallthecellisveryimportantsincethiswillhelpyou
useplaceroutetooleasilyandalsoincaseyouwanttodomanualconnectionofalltheblocks

itsavesonlotofarea.
b)Useonemetalinonedirectiononly,Thisdoesnotapplyformetal1.Sayyouareusing
metal2todohorizontalconnections,thenusemetal3forverticalconnections,metal4for
horizontal,metal5verticaletc...
c)Placeasmanysubstratecontactaspossibleintheemptyspacesofthelayout.
d)Donotusepolyoverlongdistancesasithashugeresistancesunlessyouhavenoother
choice.
e)Usefingeredtransistorsasandwhenyoufeelnecessary.
f)Trymaintainingsymmetryinyourdesign.TrytogetthedesigninBITSlicedmanner.
25)Whatismetastability?When/whyitwilloccur?Differentwaystoavoidthis?
Metastablestate:Aunknownstateinbetweenthetwologicalknownstates.Thiswillhappen
iftheO/Pcapisnotallowedtocharge/dischargefullytotherequiredlogicallevels.
Oneofthecasesis:Ifthereisasetuptimeviolation,metastabilitywilloccur,Toavoidthis,a
seriesofFFsisused(normally2or3)whichwillremovetheintermediatestates.
26)LetAandBbetwoinputsoftheNANDgate.SaysignalAarrivesattheNANDgatelater
thansignalB.TooptimizedelayofthetwoseriesNMOSinputsAandBwhichonewould
youplaceneartotheoutput?
ThelatecomingsignalsaretobeplacedclosertotheoutputnodeieAshouldgotothenmos
thatisclosertotheoutput.